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LBSALE[10]LBSALEMIXED-SIGNAL AND DSP DESIGN TECHNIQUES; B& k5 {( R9 }4 z0 n, u( _
SECTION 1
3 Z6 h* ^1 A/ n( ]; q9 UINTRODUCTION( n5 t" I a3 ]" e$ y8 e5 @0 k/ B
SECTION 2
2 G# R: l d+ ~3 XSAMPLED DATA SYSTEMS- |5 O; F8 r+ W
Discrete Time Sampling of Analog Signals
2 f) r0 |4 A. a7 }# H4 K ADC and DAC Static Transfer Functions and DC Errors
+ g3 _% Y/ j' M# ^7 z% x4 ~ AC Errors in Data Converters+ E" l, G: l$ G; t
DAC Dynamic Performance+ f3 [8 P: ~0 q6 E$ t
SECTION 3, f& o3 w. Z: K1 @
ADCs FOR DSP APPLICATIONS! i, }& d) ?" r8 `
Successive Approximation ADCs
* ~* r8 @; y& \( b( O. p7 Z Sigma-Delta ADCs
7 Y- a8 c- q5 m) q5 k Flash Converters
/ u' s2 q- N5 w: G1 T' @ Subranging (Pipelined) ADCs8 Z( y4 V! K( Y/ b/ N
Bit-Per-Stage (Serial, or Ripple) ADCs; N' y6 w: c+ P2 J3 b T
SECTION 4
7 }/ J! j+ H, }; T" T* KDACs FOR DSP APPLICATIONS1 k) [: Q9 J- I0 m- R
DAC Structures
. N+ d0 p+ r; r+ f7 c( h Low Distortion DAC Architectures, ]! M$ A) n# U3 k7 }
DAC Logic# y) ~# o6 z E) r& G& v' Q8 N
Sigma-Delta DACs. } K0 D+ d2 e. \8 B: Y
Direct Digital Synthesis (DDS). \# B; ]1 o0 R% \* E! i3 `4 e( M- T& z& u
SECTION 5
1 f* @ J* O: Q- BFAST FOURIER TRANSFORMS5 G& Y8 ^4 ^. ^) q* O1 [
The Discrete Fourier Transform5 } W& F" F( ^. N+ z0 A# H* V5 l
The Fast Fourier Transform @; }- D$ Q6 _+ [7 e. o% H5 R
FFT Hardware Implementation and Benchmarks# u. Y3 d7 a' h3 e/ p8 j
DSP Requirements for Real Time FFT Applications% \# ]# M C* l X; x8 B6 R$ O" ~
Spectral Leakage and Windowing
2 X& v- F( q. x. E0 @SECTION 60 Y8 q a8 d& s+ c4 f# c
DIGITAL FILTERS1 v* {, T. f& `7 g9 | ~( B
Finite Impulse Response (FIR) Filters
/ @& @* A8 L$ k Infinite Impulse Response (IIR) Filters5 A! I& ?, |+ J8 f( o) b5 ^ m4 V
Multirate Filters
& v7 E. e/ x# D Adaptive Filters
, u2 Y D3 q9 o6 s5 c' a2 G$ JSECTION 7
4 x8 C% G3 F( M) s* n4 ZDSP HARDWARE
- s, h. W8 N* s: P8 L1 v Microcontrollers, Microprocessors, and Digital Signal
. U5 \! o7 y- P% CProcessors (DSPs)7 j; ?! e: \, Z3 Z% u' Q. H% A
DSP Requirements# L9 Q- R7 ~) X/ c8 v5 s$ ~/ w* o
ADSP-21xx 16-Bit Fixed-Point DSP Core9 i( v g: r- O0 y
Fixed-Point Versus Floating Point/ V! Z3 W+ I: |, ~4 I
ADI SHARC® Floating Point DSPs
& y* @) ?* h" m' z ADSP-2116x Single-Instruction, Multiple Data (SIMD)* D' O g8 ^) J$ f
Core Architecture
7 C$ ?' u, f/ K8 O# l* V W6 e TigerSHARC™: The ADSP-TS001 Static Superscalar' Z/ W+ n) E2 s9 _- s6 X B! S/ J
DSP
* [. k3 }; x; q4 C6 i DSP Benchmarks8 T/ l1 H* D+ S; `. U+ \
DSP Evaluation and Development Tools
+ ?6 D7 d* [9 w7 h. D# SSECTION 8
) b: M5 P$ l) h7 ZINTERFACING TO DSPs
T* l l% H/ j: A. ^- g Parallel Interfacing to DSP Processors: Reading Data
# S+ u5 i9 R- } {) I+ n7 {8 yFrom Memory-Mapped Peripheral ADCs% K3 A, p- b+ ]7 ^! {) `
Parallel Interfacing to DSP Processors: Writing Data to( _; W9 m; _7 s- l
Memory-Mapped DACs8 W3 y: Z6 R- ? ]* a4 I' @
Serial Interfacing to DSP Processors
A8 E+ n2 n1 V* p9 \$ X' _- L Interfacing I/O Ports, Analog Front Ends, and Codecs to
- y/ `3 E% P# a- z5 b$ i2 ?: uDSPs1 k! G$ G* m# F7 B0 z w3 t
DSP System Interface) q& i" d3 S3 H/ ?2 m
SECTION 91 u# N/ ]9 I# U
DSP APPLICATIONS
% @$ B$ m: }0 ?0 [: T8 f/ J3 ` High Performance Modems for Plain Old Telephone
3 a u: c% E* @# Q* T0 X2 TService (POTS)
( b* I; a) Z( B) O Remote Access Server (RAS) Modems
, L* P7 s8 P' G: W+ B/ } ADSL (Assymetric Digital Subscriber Line)' V4 F8 L5 i' P+ ^% U% N
Digital Cellular Telephones% _/ ?( Y3 ^1 ^! s8 }4 _0 O- U' p
GSM Handset Using SoftFone™ Baseband Processor$ T- ?, ~- j3 l3 W4 C' ]' w3 K
and Othello™ Radio
! \, z' E* _- ?5 b, Y2 ? Analog Cellular Basestations! h7 {3 n# {+ x& q: T) Q
Digital Cellular Basestations) N f7 E6 q$ [! q Z$ v5 M! w8 c
Motor Control) A& Z4 j. M: O3 s
Codecs and DSPs in Voiceband and Audio Applications
& j6 p1 L( {7 b# Z- H A Sigma-Delta ADC with Programmable Digital Filter
+ A, Z- B4 H7 W4 Q' G* l9 S4 j1 YSECTION 10
+ |( l. B) g+ a3 d/ F+ e0 V! C1 ^HARDWARE DESIGN TECHNIQUES
, r7 C/ [, [8 L5 i- i+ F Low Voltage Interfaces
* x P* |* m1 Y Grounding in Mixed Signal Systems7 p, a5 {2 S0 z6 o/ A
Digital Isolation Techniques% z7 u3 o/ p% {9 r g
Power Supply Noise Reduction and Filtering5 M: t: a) Y% y+ T
Dealing with High Speed Logic. d! C9 E" _0 X6 `( X, [7 q
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发表于 2016-12-1 15:13
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