|
EDA365欢迎您!
您需要 登录 才可以下载或查看,没有帐号?注册
x
本帖最后由 hing_L 于 2011-5-10 23:27 编辑 2 V. i$ e; Z$ ~# L; @- o# K; `+ q
3 m2 @0 a- f, ?0 X+ e- m
请问下,我连接性检查的时候发现这两个错误,但是无论我怎么改动再重新覆铜错误都不消失!或者错误变成了别的过孔了!
8 J: }/ @4 X5 C# H- K
( x D/ A! C9 Z: d, r
% L# q) S2 q- Q; E- `8 Y5 ?/ G- {" R8 T2 [5 M; ?
Isolated subnets for: GND& ~6 I) e& ~! a$ @3 a
*** subnet # 1: L! _ O) _2 X; N9 s- S
HATCH OUTLINE(1894.35,1448.23 L2) C9.1 U2.79 C11.2 L1.1 C6.2 U2.78 VIA(1623.7,1490.75 L1) C7.2 VIA(1307.24,1460.75 L1) C5.2 VIA(1022.28,1482.68 L1)
$ o: s; i3 s) A4 [' S, R& k) ~*** subnet # 2
9 r( c* `( A/ eHATCH OUTLINE(1924.43,1507.83 L2) HATCH OUTLINE(2815.71,572.88 L2) B1.2 R22.2 C15.2 C17.2 R29.2 C16.2 VIA(1367.05,1749.37 L1) C1.1 R23.2 R19.2 C12.2 U2.53 U3.15 C18.2 R14.2 VIA(2159,1528 L1) VIA(2330.12,1587.48 L1) VIA(2709.61,650.87 L1) VIA(1965.31,1192.2 L1) VIA(2337.76,1819.49 L1) J2.1 VIA(2721,1841 L1) VIA(195,1866 L1) VIA(1219,1760 L1) JTAG1.9$ h0 ? ^) I) [
' x; A9 f/ e, z
|
|