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本帖最后由 紫菁 于 2017-9-14 14:38 编辑 I8 o: L! q: L' x% b7 Z% s
* @& Z: w# i. \DATE: 04-26-2013 HOTFIX VERSION: 008; B2 g: d8 p# f* f5 U
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CCRID PRODUCT PRODUCTLEVEL2 TITLE3 B/ N4 Y8 _# V* v* W2 ~
===================================================================================================================================3 N4 `3 U7 ~/ k% F3 v
876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit
; a1 f8 C \! k+ `1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation
) G f8 } \* ?4 `# _' h1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device2 {8 R2 z$ X! `$ c5 x* | ?3 b
1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.' b% ^2 S; _/ q) ?9 K. r: G" Z9 w. C
1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section
+ l) G B' y1 \7 D6 `' }1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running4 g4 g: {1 o0 L( I* E
1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.
) f) `3 p. R+ u$ B5 e1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence* z6 H# X6 j) w' z8 V7 m
1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.0 Q( Q' W j7 T9 n$ Q
1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason
+ E. A& e$ ~; y9 `* a- H1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.
3 n/ \, T& K* z3 T- ~5 Y$ K1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?
4 ^% q; P s- o$ l* E1120414 ADW LRM TDO Cache design issue
+ u. O4 I6 H, u; }/ Z, J1121044 SIP_LAYOUT SKILL axlDBAssignNet returns t even when no net name is assigned to via
$ X+ g5 u' x) b1 m1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups. r' x4 _6 S5 U% T9 n
1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it; ` A3 S% d* E+ S) H: B
1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.. R4 i y! s+ B8 t) {
1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced
! m) B$ m; o' o( m( E& q: R5 L1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.
4 O" S( f1 t+ s1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable1 S# g" H% L2 W+ j
1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file
! T* p/ l3 w& J! B" u1123816 CAPTURE PART_EDITOR Movement of pin in part editor
8 X, D. \. w/ Z) W& A/ k# f! @1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50
% s7 J& |8 J/ z# S8 iDATE: 04-13-2013 HOTFIX VERSION: 007- k. _& ?1 Z5 B7 O+ M, B
===================================================================================================================================
5 ]) V9 W5 ~8 k# j6 w+ h3 G& ]CCRID PRODUCT PRODUCTLEVEL2 TITLE+ P) C9 f# k* l9 k
===================================================================================================================================
4 b# n/ ~: n4 O- @: }/ d% S1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die! d2 {: [' U: O: i& \: `. l
1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6# ], ]# p+ F2 v5 A9 L; L5 ]( t# R6 ~
1112295 APD DXF_IF Padstacksї offset Y cannot be caught by DXF.
+ ~+ G' w; @, |. k8 l! A4 s1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components
' N4 R$ |4 r+ n1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
: u2 N1 e4 u! `4 J$ f' c' g1115491 ALLEGRO_EDITOR SKILL telskill freezes command window
6 t ~) K% d5 v2 ^1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
! N& z+ B" f* p; S; P7 |, B1 K& T# J1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.1 n3 S1 Q+ b. N5 |4 B
1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear
6 C( l* R7 O: K& V6 ]. f1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks3 y7 {: Y/ b# e7 ]+ \- {/ b7 }
1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?: ]+ u0 R' E+ H5 i1 k, Z/ a
1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh
9 H% [4 k. |3 v1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh: R6 B9 |3 w3 n4 k, s: Z
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors V( S2 T- s4 a. d. T
1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.66 m! G+ r7 x# {! @3 x
1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently6 \8 s5 @/ b( Z; [
1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps
# K9 H( D2 H8 J( ]2 u o1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks% s# f9 r9 r% p$ l. @
1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.$ [; M. B" p+ D/ Q2 R
DATE: 03-29-2013 HOTFIX VERSION: 0067 ]" o9 i0 {6 x( ~. P
===================================================================================================================================7 M8 O2 i$ T6 X7 n( s5 P( R% _# ` H
CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 U1 _$ \9 |* p$ r% J* |# w===================================================================================================================================
1 m; c, O/ Q7 V% v4 L110139 FIRST_ENCOUNTE GUI Error in Save OA Design form& [+ r# [. I' D2 U! w3 u+ Y7 O1 ~
625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.% w/ ^+ O' y7 M- p3 X
642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep
' L/ w+ k& K- |" F& S650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".
) c) r7 g$ n% k _$ x! v653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend
4 i0 g I ^$ r; ?, O# p& B687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect
2 v# r: L9 T) _( T6 t& K# G- p787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics7 c% Q! ^' p- a4 U/ }
825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
% }$ \6 j- o* s834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
% u5 E" v, x5 A* m: y& q835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
( d8 ?2 U8 v% O# P) y, E868981 SCM SETUP SCM responds slow when trying to browse signal integrity+ ~1 O$ ?1 j0 u) _7 j
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
- E' O. a' y, V/ X5 l873917 CONCEPT_HDL CORE Markers dialog is not refreshed6 T) S; I9 o2 W* F! A
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License9 M e" z. S) S& j, o8 ?# j4 ^. a
888290 APD DIE_GENERATOR Die Generation Improvement
- h5 b1 o/ F, @* k. \892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator( F. ^% c3 t7 @. w& V- y9 F
902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice- v* X2 l! | }9 @+ U# l- U V
908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM4 J# f) k' E9 _- |4 `6 O# J3 }9 Z7 n3 k
922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols
. S( e( O; z7 `* b9 D! m9 R923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences
* a' A$ R- \! |8 g# h/ P1 S935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC
' z V2 ?+ i$ H- h# G& i$ K5 u9 L945393 FSP OTHER group contigous pin support enhancement' T# }' X* y0 A
969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database0 X# ~ n4 F5 b4 g7 E/ i4 }; o- L
1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes
' ^) w$ a+ x* `# {' ~5 v- N& t1005812 F2B BOM bomhdl fails on bigger SCM Projects
- C6 j [1 e7 `' a. R! ?" a1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture
# X" P0 [+ A# ?- Y1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names6 H. q2 \: M) J* M
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net
) P$ e8 y( p/ I( I1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
* H- X0 d& J& f7 z* t1032387 FSP OTHER Pointer to set Mapping file for project based library.
) L& ?: f3 K, `2 u1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with ї LL PLL_3 does not exist in device instanceї! I& }7 f4 G! [5 ^8 S; ^& q0 a. t
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart' q d/ u4 [0 S3 B n7 k
1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding( R: X C/ y9 V" s' P( s
1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.% H' S- A2 k7 \- P
1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
; n; B1 t/ @6 {1 ^7 t* |1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll3 X C5 W; Z3 H' r
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
2 b; H/ ]) i9 x! u* T7 I( D' c2 a1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects# l9 d( |! ?7 m6 w
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus
) ?* Z, X7 w* |* a5 L9 K; {1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts
/ \$ P9 G U5 @1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs
' _% B7 W& b8 B; ~: \/ p% P1065636 CONCEPT_HDL OTHER Text not visible in published pdf/ U" z7 t5 f. y
1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings/ P, m3 y- o4 ~4 T3 P
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary( B2 A- ^. ]/ G5 I& t% G
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
# w2 ]- p8 E3 a) C1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic; E7 U, z% {+ T& [
1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down6 H* P z9 \* I; l- h" E
1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45
) U1 a& @& Y/ J/ J, j6 |1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal
9 g/ p# \3 C- h$ U8 L2 _1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check0 b: H' u( o6 ~
1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.+ r6 ?4 I2 S9 I* u! X
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)" }3 \$ B9 ]. u! D9 ?' z: |8 ?5 @
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die7 g1 d0 l# y+ F. Z# o
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic$ j+ E* p4 P0 e9 F; H
1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
: Q9 [. t' K. G* a3 H+ A; |0 Z$ c. @1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects
/ j) X/ e7 ]: M* L0 f1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format: }5 v# q$ N+ v; p
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net6 _% A/ r$ j/ n4 V* c3 L. a" x9 |
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic5 M$ @7 _2 b8 u4 f
1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
$ n9 D7 u" j; y1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.% \0 a5 y" d( e9 s$ Z
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
: c9 f4 o, v1 z+ s1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors& ]' h4 y' N! ^% ^4 R1 O
1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.- `+ y: @7 y2 m; }$ F
1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition' w6 ^. r; E$ n
1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor. e% ?7 l( r1 _) }+ s" p. ~
1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options% G x9 r" f, ?
1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5
, `6 M% M" J4 U! @6 p1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.& C6 w3 C6 |) N* b8 s- z7 O1 B
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate3 b" s$ A" Z# _# j
1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
H& G9 X, r1 Y( s( o+ M6 P1078270 SCM UI Physical net is not unique or not valid1 G3 n/ ~" i* n& |+ J
1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted
4 S# ~% G" `) U+ L0 i1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle- M7 `; Y. d! r D
1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs
& c1 \( w9 _+ O) h1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage", _0 W2 a' r5 \( c9 x
1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters9 v; m) r& f$ D0 C; ^" H: K
1080336 CONCEPT_HDL CORE Backannotation error message ehnancement
. E5 F. u4 h" n6 ]1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license1 o" N' L- Y$ ]+ j; ~. K# D, o8 U" H
1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd# k+ x% e7 \# t- V0 g9 h7 N2 D
1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error5 ^6 H$ X9 v+ \
1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.) m' j: l. }7 B7 S
1081760 FSP CONFIG_SETTINGS Content of їFPGA Input/Output Onchip terminationї columns resets after update csv command% F$ ^$ o0 k; e5 h" g' ?8 z' @5 K
1082220 FLOWS OTHER Error SPCOCV-353. r# q2 k( ], C- E2 y
1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.
9 l; ^4 `1 o8 K4 u" h2 a1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command& D! c* x- }0 Z5 N' {# ~
1082737 CAPTURE GENERAL The їArea selectї icon shows wrong icon in Capture canvas.1 a6 i7 {0 @8 _0 [8 t: M. e' u9 W& L& s
1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name
: _, w! F5 U& _* m% G) t1 o1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way
0 ?& Q* g s: D }2 y1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher
1 o1 R/ E- \0 Y1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI
" q0 i o' H7 K2 `7 m3 b1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
, m/ X$ f' z' k8 p1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.( I! D: _2 z; E9 ]7 b0 V9 \, a
1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates! Q0 z' c3 D9 |9 X6 C
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters0 V2 F4 \5 D: R* Y" @- t7 b$ Q4 t
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.
9 d& C/ Z4 K9 K' C+ @1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results' _7 t" E. y4 c' h! W
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.( T0 d* p& B9 S& n! h( ^
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update
9 S3 V# c$ J' Z4 q# ?6 h1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO \4 n+ D' c7 m+ d* S z7 S
1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working' E# n, C- ]2 x
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.# U; q. v/ _4 Y7 E
1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design% o( A( M7 U, m: _1 a9 y
1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated5 [5 b6 l0 J; n
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins: O- M6 M' i$ A
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity! I, e8 ], U* \! M d- w) A4 _! S
1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.( d; r" f2 _) }
1087221 CONCEPT_HDL OTHER Part manager could not update any parts.8 U9 _4 X1 C, f0 t
1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space
* v- E2 p0 s2 U+ v1087295 SIP_LAYOUT EXPORT_DATA Enable "ackage Overlay File for IC" for concurrent co-design dies too
; Y- ? h$ v% W4 k) G7 R/ ?% c1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice
2 p! A2 E3 O! [$ h6 h1088231 F2B PACKAGERXL Design fails to package in 16.5
9 ?% r5 S! P8 q5 V0 q. f1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.! d6 u+ j+ v/ e
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor
/ \) O2 o* `5 c Y5 B1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager- H/ h1 t0 M0 N+ m
1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?
3 S1 s: ^9 `3 Z& z6 D& J' C" U9 F1089259 SCM IMPORTS Cannot import block into ASA design
- r( t% S7 ~$ d# {9 s* Q1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form
& K+ l* `+ R$ L$ o& I# C7 n5 p1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project% A& g% G. Z5 ?' j. }
1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory1 R, i: r, w7 ~0 J. @1 I- u6 t
1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.. Q4 j: q" w- H# D0 ?) J) ~. V
1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB1653 u* ^9 d D% ?* R
1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.: U7 x8 p0 |" x9 T1 i
1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22# R3 K4 a% p4 q% f- u
1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.5 V9 |5 ]- y5 v; V7 x u. P
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.) w; T4 ~! `5 V8 q4 c
1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled
5 o) V. u" n* J# M8 [, C1091359 CAPTURE GENERAL Toolbar Customization missing description; G3 g& `4 z5 m0 D7 C0 o
1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
- W& |4 [2 ^ H: N: D1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time
8 T4 |, p+ j8 R; _% ^9 o c1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5/ P N2 ?. u0 c# ~6 y$ `( J
1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design
. ~7 K/ T4 h# f$ e3 O" u1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled
+ {; Q6 Y0 y: x/ z# i- q: v1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters
- G: I2 n# q6 Q+ E: V: k1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error% D/ ?6 G; E2 [- Y
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder# c8 R6 Q( {- ^9 c1 N2 t! Q
1093327 CONCEPT_HDL OTHER Getting error SPCODD ї 369 Unable to load physical part in variant editor3 A/ O% _7 V$ b, p+ B' p+ z
1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
& V$ F/ h4 f1 X' J2 F1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time
& A7 F9 L; D2 Q3 Z. @1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.
9 Q+ A& z! K2 S$ n- Z: [1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
. s4 _6 x* _7 {' q% G1 E1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic
G* A# j7 n i; [- u1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
9 a, B" O. f! }$ m3 t1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet
3 ?8 F/ _. |( n5 v4 P! _/ q6 V5 _1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die% `' l1 D! T# f4 ] i7 ^. |+ l1 j7 [
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block. V2 J. ]6 |- U, I
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
# u. {. d3 @; A, d4 W! Y1095861 F2B BOM Using Upper-case Input produces incorrect BOM results/ N3 \# B [0 E$ F7 s
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import
; c0 a+ q% R. q7 w" |, [1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically+ C u0 e. N, b/ t7 W
1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias7 {' I9 r) n- a6 V
1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate
# ~ B& O i5 P+ D' O/ ~7 y" i1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors# `5 B% g T0 d4 Y _0 h$ s
1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL
" B8 D: w2 `* z. H) [" ]1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.
0 m2 ~. S3 {9 O1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side+ G2 J% @4 e4 x) m. _
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command
" s1 y3 M5 E7 k# E! Q1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
6 `) M6 J/ N- s8 X# J+ v1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives
& ~- A; E# U7 I4 I1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork
}1 g, G2 l& A) k1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts3 x8 a1 _8 T" c% N: s
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy- b u( M8 c$ R% W) D
1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.
% V" ~2 v! e1 S$ b$ v; L1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties0 n& p$ \' h) ?! @. V( q& Y
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6: P# C+ ~- D9 X( h0 j. C! |
1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad
c- h1 f3 A5 ?2 }8 w" ~" i1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3$ R1 K% R! x7 g9 G7 |" s* I
1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad0 l* D9 M D: |& {+ C9 v+ [( _
1103703 F2B DESIGNSYNC Toolcrash with Design Differences# @/ e8 f2 F' a0 R. M; C
1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view
# g% e' z6 Y) i0 [1 Z3 t- W2 n" `8 A1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6
$ L3 Y' M: S! W; @ Z2 q) ?1104121 PSPICE AA_OPT їarameter Selectionї window not showing all the components : on WinXP& T$ P7 Y3 ^8 `3 o3 _
1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly* T9 S: w5 _" [# o' K
1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM
: ^( O! p" C j0 y4 f# m0 u- ~1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.
4 K3 H0 W$ n" V6 g# A% }1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.) W& h/ X/ B5 h- E2 {
1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form7 D$ P, g+ b* S8 b- B( u( n- U
1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
, F, W0 I7 W. J1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked
! D% H7 l5 B- G l$ C) U3 j1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
3 T8 c7 t! M3 r# {# ]5 E1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6
* X$ g$ B @ f5 c9 H1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only) t4 `( e6 O. c# H' j
1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid) d, h7 W( w) N+ H
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.+ @- O* \, {- r# D! h' ?
1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param: I$ P3 F' O/ C# L; s+ s' J
1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish
2 j7 `% v5 |) R9 R3 |; q0 v1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).8 o! }2 q+ U& _ O8 ]! H
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke) u( ]9 W/ k0 {* e) w
1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.6 z8 u( y/ ~% R
1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode
0 Q% |8 y3 ]" q3 g0 L1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs% S' c. M, ?( C- n
1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6" H u# h7 b1 O3 ?% y7 [
1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.
% w- e" }5 q) w- H3 T1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
# |6 E4 r2 v9 v( X& j( [- S [1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
' w4 h9 i! |' I- K! }1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset1 f: q; F! y+ e9 t# a
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters
% w! X; Y q+ v2 m6 e! g$ j) F# G1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
8 i$ s9 P' v. w& B% l1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP' p, w, k7 {' x G- U( L
1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint
8 O( q* j7 I0 d* I' G) Q1112774 GRE CORE Allegro GRE not able to commit plan after topological plan
3 o( W* l2 X: b5 Y2 c r- k' E1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color." w8 @/ A% ?) }) [" T9 l
1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file
. w6 B8 W2 p- o1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6& I8 k( M5 x3 o5 I
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发表于 2013-5-2 11:34
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