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本帖最后由 紫菁 于 2017-9-14 14:38 编辑
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" I" ]1 z* Q; @, V0 ~+ H5 w2 sDATE: 04-26-2013 HOTFIX VERSION: 008( N# w: L- U' d7 K0 l; J1 A, g7 R
===================================================================================================================================
" t0 _! J, w/ R6 MCCRID PRODUCT PRODUCTLEVEL2 TITLE% F5 \, K U/ O( l% M6 K
===================================================================================================================================2 S6 o& a3 m2 c7 ?8 R, ?
876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit* Q; F ]" `& T6 X
1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation
: N: J! x5 k2 Y1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device
. m! S# U' t7 |7 S6 O' X1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.3 u U3 T' a6 ~' G2 H' X* H2 t/ k
1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section1 C. d- S8 m! i8 n; x
1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running
& ~, p: i# d2 \& V3 z9 {- Y5 M1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.8 t+ F: v* j# W; J# r
1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence1 X, G1 }) z4 ^
1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred., c; R. e# v/ W7 h/ Y
1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason
& P. E/ T! M6 W, Z1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.6 ?# X3 x8 f( j4 w
1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?
, \- n+ }( C+ `% I4 t1120414 ADW LRM TDO Cache design issue6 I+ U! e! |% d0 P8 I
1121044 SIP_LAYOUT SKILL axlDBAssignNet returns t even when no net name is assigned to via
5 U8 D7 r6 R# X9 x1 ]2 x( X1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups
* E0 ]' K# a, ]: ^) X$ ~5 |1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it* @. P7 O5 ^4 j3 A
1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.' M3 L, T2 @4 Q/ n# ~+ q
1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced% d q# D! K; G5 H
1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.
+ r# ^4 _: I& \, m, O' Y5 B1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable
) v0 w! V4 `8 q6 d) Z1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file+ M) z' l, o5 ]7 t" v
1123816 CAPTURE PART_EDITOR Movement of pin in part editor! Y- }& ^% j' m) ?; w' ~- c9 l
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50. t6 W2 Z5 T0 ^7 v$ Z$ T
DATE: 04-13-2013 HOTFIX VERSION: 007
M/ f6 {; B! _ q" A" U===================================================================================================================================7 r8 ?" u& D4 e3 z+ t- p8 b9 c
CCRID PRODUCT PRODUCTLEVEL2 TITLE
! v( o5 Y7 a5 Z4 ^8 q===================================================================================================================================
$ r; H6 y0 K. j. ~$ S F1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die+ ]! Y3 k- m$ L& H3 e4 u8 ]. J
1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6
5 L9 V' ?# d+ Z' G. C8 t1112295 APD DXF_IF Padstacksї offset Y cannot be caught by DXF., [' b6 l0 d2 n9 c/ N" K3 W
1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components
5 ~' K7 q. B! m( L' o$ x% ^1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
& p) Q, q8 T( w1115491 ALLEGRO_EDITOR SKILL telskill freezes command window$ F0 O) |9 \" c
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
1 B/ C/ \9 K% J: A1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.
C$ q: Z- N! E: i( H$ T( j1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear7 J3 M& f* F( {& w9 ]
1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks
?2 [ M& d. j' [1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?
3 G) _' s7 o5 E' V5 [% O1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh g1 k% f- D6 P" v8 E7 X0 |
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh
8 b4 ^$ E- l$ L( w8 I- i1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors0 j- x! W% M/ e5 \
1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6, t4 f! A! z; h2 R, w7 `
1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently
6 n4 |* }1 g+ q- d3 l1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps
* W, P4 ]( S& g# a! ~! q l1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks3 W6 [7 p ?. G' D
1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.' }- _. v8 R- A" ~
DATE: 03-29-2013 HOTFIX VERSION: 006
. i# |2 Z/ p5 ^% T; s2 j, S0 i=================================================================================================================================== b: |' X& X2 z6 `
CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 \' _- [9 ]# r, j===================================================================================================================================5 @# M6 Y! b7 p; _: h+ `' x5 g1 P; G1 V
110139 FIRST_ENCOUNTE GUI Error in Save OA Design form
2 N2 o9 Y# k' @- n625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.& g6 P4 e( c) U/ d e: H
642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep7 }2 }( h5 F, g
650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".
g' U/ p) {$ S) e653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend
% G) H$ C Y- v& s" S, f, T687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect& g/ y2 A3 L$ U2 M; d
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
8 X3 Y) _$ i. e2 q825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other" g- a2 p2 M) Y+ Z$ w' n
834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
9 {. V5 ?* g+ I/ n) C4 W h835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.; v/ T5 Q( m; s8 r
868981 SCM SETUP SCM responds slow when trying to browse signal integrity3 \3 C# z, q* ~0 @
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide6 J8 K! w! k6 ^9 G' \
873917 CONCEPT_HDL CORE Markers dialog is not refreshed
3 ~4 [3 x/ X- G0 n& A887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
/ D" R& I) R, I h888290 APD DIE_GENERATOR Die Generation Improvement
- q, M, N% ^8 b& R; ~892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator! U4 H: ~+ e: I/ E! C' M: R; k% {
902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice
! ?( h# C: O2 j4 v& b7 x) N908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM9 C- ]7 E" U& k) L8 ` m. W/ ]
922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols0 v; ^$ z0 f) j- C' G' L
923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences
~7 ~) G. R/ a- i& D' J% ?935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC
0 J5 C7 b4 D' w9 Y0 c945393 FSP OTHER group contigous pin support enhancement& C: C* R, M2 V
969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database
# |& _8 Y+ t4 D; b! t1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes3 `3 F s; a" d0 F6 h
1005812 F2B BOM bomhdl fails on bigger SCM Projects7 \$ M* L2 h E7 ]9 ^" `
1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture
2 k& i/ b3 [6 h/ V% I1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names' Q* N* |: i$ q( R. G7 H3 H
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net9 V+ f, s' }) N7 d
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical5 [9 ]# S+ t( Z) Q
1032387 FSP OTHER Pointer to set Mapping file for project based library.
0 k5 [( x& c3 G* T+ J1 G4 U1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with ї LL PLL_3 does not exist in device instanceї
3 C( C6 n9 N& ~' V) n4 g. P: m; R1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart: [; s- @2 m7 r6 |4 h2 D4 ^. J$ k
1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding
5 F; q5 y S. g1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.' k0 _7 p+ b9 z. y- \2 R
1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
1 O) m9 K" E& \7 J0 ~; Y* E3 q5 o# x1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll
" p/ T/ V$ W/ Z" v7 R6 l) b1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation& R. g3 M" U2 q* s! G
1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects' P9 v m8 q. X) M, r- T* w
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus
% w5 s7 f4 W4 A3 j p, b1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts
- R6 t: r i8 J! I1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs
$ R- P9 T% {4 |' N, ]1 P* q( M) W1065636 CONCEPT_HDL OTHER Text not visible in published pdf
; k5 k/ [: W+ S( P# k1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings2 H J, p/ S/ R, o
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary
& a6 }! F/ c! P$ ~1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts9 f: r& W" e/ o3 @9 _$ t% S" b# v( i+ @
1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
: {+ [. J; _* W9 V: a4 r4 t1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down1 s6 E( \7 j p) L$ L3 f5 r( ]0 ]
1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45, s, r; |& g' y! s" p
1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal1 s2 E) l2 v/ p5 t' I$ K, j% Q0 h
1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check2 s6 `7 w" M- N
1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.
) _* d1 A& ~7 Q u1 ^; n+ q. E7 ^1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)$ L/ w7 I$ \! w' x% O) j# @
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die
- o. Q6 |' r+ e! M) N* L4 z7 t1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic4 l q3 E- f$ K, p) z! @& d
1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut) G5 ?% [/ R- i8 l1 Y3 V, S+ C
1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects5 V2 i, ]" ]; [- {
1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format& \3 [( M0 V9 F: R; n
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net
- m& I( E: H; a* x: T) P9 @& F7 g: v0 w1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic g8 I7 v; b0 b9 ]- z" A
1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
7 V! U% c. {) R6 n# Y6 M9 Y1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.0 ?: v: h9 D4 K: s& a
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
+ E5 S9 u R. Y1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors
$ \2 j' x" k$ z7 Q& J* U: ?1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.
( e5 Z: o! N7 G7 {9 \: x3 L2 P1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition% S1 T( Y5 g, W- f
1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor; k& P' J8 w( ~. X
1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options; c2 Q9 t5 m" E6 J- b8 p$ [9 Z3 W
1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5( e9 |4 G3 b$ d- n
1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.% P4 f) h6 j' n: c9 U5 [
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate# U: ?' o/ F0 J) x k/ G; p
1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 30 y, k! \0 f+ K3 V" U3 M1 a& O
1078270 SCM UI Physical net is not unique or not valid
& C. j& _3 S5 a. v2 O8 ~1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted0 {/ n# z3 z' g, w4 P/ u% X% ?" P( X
1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle1 h2 a7 A* D9 i! f! j
1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs
" L. y9 ?4 C) X5 V1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"
1 Z* I% }1 e/ y% H3 g; {1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters
. T! V2 K1 C- I/ Z6 s1080336 CONCEPT_HDL CORE Backannotation error message ehnancement
2 s8 {6 _0 T; o5 R; G: N: v1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license! @" P$ B/ [$ c& C6 w
1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd
& h) C. x6 z7 n1 T# S$ S! m1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error9 w+ o$ P4 a* S3 P7 j* o' p
1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.
8 O6 Q/ C% g7 ]! l" N1081760 FSP CONFIG_SETTINGS Content of їFPGA Input/Output Onchip terminationї columns resets after update csv command6 W! C+ o- U; C* q) |( Z% E7 a( O
1082220 FLOWS OTHER Error SPCOCV-353
. M2 ^, K7 l- c6 I+ Y# C, |4 f8 g5 L# m1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.
: i9 Y% N; _/ K( f( L- m1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command
O- I5 K, T* ]1082737 CAPTURE GENERAL The їArea selectї icon shows wrong icon in Capture canvas.
5 ?9 a9 `. i/ y: B' c# e1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name
S6 Q: W0 b! J6 c1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way
: v) K. n# A5 @3 Q: z0 z1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher% F$ w7 ^* U0 s' R
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI
+ y% L$ A& S5 t- X: Z) p3 D1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file0 ]1 [: I5 G, r! \' K0 \* f' h7 R
1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.
- Z" u+ }2 i/ o1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates$ y# |' \" v3 h/ g. l
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters
& F6 q2 p2 ]" Q; S, `1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.% f1 e& Z' b: y; w
1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results
( H2 y: ^( h9 s& G9 i2 j4 h9 W; {1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file./ W0 m0 h9 z3 j m- |2 S, z8 g
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update
% }( I6 q0 v- x. L) j1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO3 }% X" Y+ E+ ^
1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working& w, k/ M) S# p" G: |
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.5 [( { `, j& Z3 w2 r: m7 e5 w* h
1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design1 a# c `& ?4 V8 o: o" ~9 n% y
1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated
. _+ {: v9 p) n1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins
+ F7 Q9 i. t. e% J8 f1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity
2 B8 r( l s- e" g* _" R: D8 l1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.
- Q: r% H# i: {8 P5 V. {, e3 G; z, q1 \1087221 CONCEPT_HDL OTHER Part manager could not update any parts.5 j: p/ J* U3 x
1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space
X4 x/ d2 m9 \4 L# Z% r8 `1087295 SIP_LAYOUT EXPORT_DATA Enable "ackage Overlay File for IC" for concurrent co-design dies too
+ ]" U7 @+ Y' n9 S1 ?6 N+ m9 i1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice2 t* X9 ^8 f- t4 F- m
1088231 F2B PACKAGERXL Design fails to package in 16.5' f+ Z" K+ m' j8 e" [! ]
1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.; q* N; v# ?: M+ N2 L( v% L8 _4 b
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor' p: G9 X7 j8 b+ v2 E9 s
1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager
% k$ \: L& k. z. _1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?
d, F) B2 @) y0 N6 {1089259 SCM IMPORTS Cannot import block into ASA design
' h& M9 N. l! f$ U* r5 q0 W9 N1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form; P- P3 u/ R0 F% D
1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project
" I; a3 A9 a. L- Y5 ?" J1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory
, X3 b+ r% I& q( ]1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor." W" C7 _. I3 b+ n: F0 F% @
1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
* L! m" C( s) Y: c+ j/ x" @1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.
. Z/ ~. z. v x) F1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-229 w$ @; ~9 `( w% h5 T
1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.
( ?& A# Q" \$ E1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.5 t' k! f; u2 v2 b
1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled X2 ~2 Y! | i5 {
1091359 CAPTURE GENERAL Toolbar Customization missing description
4 \9 P% {( g& j; }* `4 B& h8 P$ y1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive) l+ n$ U) e# h) e5 w( a# W- _
1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time
1 _ y. N* Z1 G" q1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5
( J4 x+ j1 U6 t1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design
" h4 N- d6 K# Y s1 L1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled
5 P; J; g, U: X1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters& m; _# e2 R4 p# R6 u x
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error
0 Q8 B1 H/ @) Y2 r- r- N1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder
, i) W& y% i+ E C+ v1 E4 w1093327 CONCEPT_HDL OTHER Getting error SPCODD ї 369 Unable to load physical part in variant editor
( u) R6 f# {0 C1 |2 _1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
$ M' E* _, }1 ~' q: P+ }; J% _8 f4 G/ B1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time
+ V6 Z. }4 D3 n9 Q. t5 Y1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.
# w' X# M# O; \% W* o1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
$ U6 {+ v u; e& }5 y7 g1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic
* w3 }5 I, c: ?4 v: t! j. ^% Q1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
R; z, ?" H- S7 A2 m1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet
$ U* n) R* e) \; } Y1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die
6 w0 m* _9 U/ t o9 L) D, |0 q; z1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block5 p- f1 d5 _9 y1 ]6 l
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
t" }& W$ u6 D8 ~1095861 F2B BOM Using Upper-case Input produces incorrect BOM results% D6 J# h6 {/ m, e) n' p- u
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import
% |$ _' Q5 x: c" R1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically* a& e# z8 ]% \( b4 z/ u- ]
1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias& U, W& U% s/ f$ U: p
1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate
B k! u; z& p5 H" {1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
0 ^% n8 S+ Q1 U* H" e% [8 L1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL
# a5 c( Q7 x: H- ^9 {1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.; k! U! i" V/ ]. d
1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side9 c7 H: N5 u- z9 T3 c
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command" l. g! d' K5 w1 E/ y( @
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character. [# G/ k1 ^3 ~; o5 y6 G, v D0 k
1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives9 Y* q& ~6 T. S* H1 x; W0 T& e
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork' }+ F% x# o% X" @6 v/ G
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts# ?, {4 b3 p' r0 K g
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
6 O9 p6 H0 z4 M0 W1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.3 q& {2 {: Y" c
1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties0 l8 A0 } B0 W. {
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6
- k3 B& b# n2 F0 G1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad8 H) ~. Q" W0 C3 U+ Z8 D
1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
0 v# E7 s3 n. i1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad6 F+ C* S; X7 k: C( U% D. Y( M
1103703 F2B DESIGNSYNC Toolcrash with Design Differences8 g& k& Q2 i/ W! B! y5 W
1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view) X7 ^& V' M2 k' P* m
1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6
, w* A* F p8 l/ E' P4 |9 `, [* h1104121 PSPICE AA_OPT їarameter Selectionї window not showing all the components : on WinXP
s% n; _, |# S( [8 a! |# S- J {1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly
$ A$ k& ]6 `- l1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM3 ]; Z% _3 K, }' D6 J: g5 U
1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.
+ f7 W k0 R$ Z1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.
/ g. v& Y, I# y6 V# K S! p9 \1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form) m6 a+ Q4 v- o% q
1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
# z- I% |$ I* d% H& X0 { ~! o1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked+ j( `( j$ T4 V7 s. B: }
1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
# I$ Y I, F" J) q: e' Y1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6; o& a) Z9 z/ |3 t! X+ w) d
1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only {) g0 y4 }* ?1 E
1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid
( ^5 i, a- j/ D+ `# c: Y1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.( u) Z/ a+ P( }* b
1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param5 i2 C4 [$ q( e
1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish$ n5 Q" w: e- h6 P* X3 Y4 i
1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).
) v/ z4 g/ ~8 B& G* f8 t2 [ n1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke
6 }/ H0 N; w2 L1 _/ S7 l# i1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
% x# p* y7 [& J: t6 Y1 f. ~" X1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode3 p3 E$ ~- |: m0 k& h1 a
1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs
) g, ^8 w5 ?: g, n$ \1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6
3 ?7 ^( ]; c( }3 M1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.* W5 ]$ ?7 {* B: I
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
7 d M, D! y# k3 ~1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
2 }0 S8 h5 ~4 i) R1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset
7 _" B6 y% H. t1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters
) Q0 Q0 w9 p4 X( u1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend+ Y0 u+ |% M+ M6 r; F
1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP' ~+ r v+ d' b( b3 n1 J: e
1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint
$ b) \4 ~; l! S$ P1112774 GRE CORE Allegro GRE not able to commit plan after topological plan
3 G" s: q7 ]& G/ f7 d# U3 a4 h1 v1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.
2 H8 n3 w' q0 w/ Y7 a1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file
' `7 X- V1 D, I* X. f( |. ^2 o) i' t1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6
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发表于 2013-5-2 11:34
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