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本帖最后由 紫菁 于 2017-9-14 16:05 编辑 2 X+ U `% p5 f0 F
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转 Hotfix_SPB17.20.015_wint_1of1
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Fixed CCRs: SPB 17.2 HF0154 S. A! t; n. E( {9 p
03-16-2017
% u: l% z9 C W, h% x========================================================================================================================================================
W9 r/ w0 e f" |; S8 QCCRID Product ProductLevel2 Title( I3 [% Q! z7 i3 T" S( t7 [ J8 T
========================================================================================================================================================4 {" p! D! P/ c9 b0 \* C
1653366 ALLEGRO_EDITOR INTERFACES Unable to attach step model to symbol
. m8 |, T. D; A A1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model1 D5 |" p' l9 U3 ]
1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function% g# A! a2 O9 D/ g& Q) M
1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file7 Z* I$ p$ P; }: q; N4 M8 O. z
1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting Padstack Editor results in incorrectly scaled forms* |3 R, j3 O( V$ v
1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design
# N* a0 l7 a% A. N2 S/ j1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees
& M) u+ X% I" M/ h1 K5 L$ K ?3 S1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.6 c/ B: }( T/ p$ b
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
& s$ K6 e2 J/ k: @# V; j/ c1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor: M: r# ]/ r8 G1 k' h# k+ ]0 l
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not- v& C: n: p" i
1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used- c m8 h' O; c" F* L# A4 b! ?% O: n
1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places
/ I1 \/ z! n/ n6 L8 X: {8 I7 _1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value2 B" y! @- b5 h+ ?9 N
1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically w1 f8 W2 [) O3 S1 B! y* I2 ], Y
1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad
, U" N+ r8 G) x" t( [1 c3 r7 R1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout9 j3 b7 Q4 V F! c( }
1698697 CONCEPT_HDL COPY_PROJECT Copy project corrupts the .dcf file' L- h! K P* A( l9 @" I
1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084
7 U# @6 q0 T3 U( u, ^. ]0 B: q* _1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position* ]8 m% [) G" r% ^
1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net
6 X8 j6 A3 M) d& b9 W1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer' [1 |$ {# r) o1 e$ E, H. r
1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation( q/ d$ G- W# ? Q- e
1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
$ Q7 C) h" B( s" M. v1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode
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4 Y# E# Y$ {, O6 g' Y9 O1 O; I转：Hotfix_SPB17.20.014_wint_1of1.exe 链接：http://pan.baidu.com/s/1jHFB2Pg 密码：mxnk F; `+ x- ^5 l( S! Q" W- ~
Fixed CCRs: SPB 17.2 HF014$ ~! q A6 d L5 u* X
========================================================================================================================================================
@9 ?6 M, A4 _CCRID Product ProductLevel2 Title
. n7 O, Q$ h8 y6 o========================================================================================================================================================+ i9 j @. H8 R1 p$ _& I- ~
1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships7 ? r2 M8 B9 b
1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity
: W, G! P5 _$ n8 H1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-268+ ~4 @9 s8 y; T: V6 i
1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data
5 [) z9 G" J! K' n/ I/ `4 {1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data8 w h, v. r1 p9 v
1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors
& A0 o N' k8 N4 }: q1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.$ ^6 {9 B2 A' J0 g
1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted. r& [7 n# \1 t/ z9 r
1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location
& `! k/ A: E( D4 G+ i1685995 ALLEGRO_EDITOR SKILL All film sequence numbers are returned as 0 when using the SKILL function axlGetParam
$ ?' g& i5 F# ]6 M0 R! B& B1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately
" _5 b, ?+ E* I% j8 U6 T1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6
1 K- y: @2 ` k+ u5 F1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one4 u0 d4 J Y0 o6 `
1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled- W- ]- q3 {% T& y$ k: @# e
1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved O2 w; o( @; g1 j
1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components$ u/ _# ~" \# W$ W, z# [7 V% R
1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers7 p: o' t$ Q( D& Y- @
1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase" c6 f" t. T/ h+ n
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement$ B. v* p1 i; D7 U7 z
1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message5 S J. p+ R z8 {4 @6 l
1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011
& A- ?1 m1 E; m- f1 S1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2 i$ m1 P2 W! H, Q: g
1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers% q* {4 z4 m: ?4 H
1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016- N2 e- b6 J: l1 h3 ^
1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design
* o3 X1 w4 b( R6 p0 w3 P1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors+ k$ e1 Q1 S1 H2 r) g7 c
1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters7 g& P5 [: r" K, D
1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP/ n, K( p, u- u+ Q! c- p
1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'
6 P a# s4 @! Z& c. Q1705265 INSTALLATION DOWNLOAD_MGR Problem installing OrCAD Library Builder from Download Manager/ ~+ G& {3 C$ n
1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script
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4 O$ i$ {( K% _; ACadence OrCAD and Allegro 17.20.013 Hotfix链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv: {% }* M) C& p2 k' H# p* z
Fixed CCRs in SPB 17.2 HF013- b1 K# q5 y3 ^
========================================================================================================================================================
1 h% K1 @ p' HCCRID Product ProductLevel2 Title
: H- \' b+ @# v6 ?# E" O========================================================================================================================================================
$ k5 z* d, o) x0 H) _1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm7 P" D. s' I' i4 X) @6 D. A, Z9 f
1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer
' A: Q u2 C6 c/ O; ]% P1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version, e8 j- v( C ^8 j
1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated
% a0 M B( ]: y+ m/ |0 c" j1 _1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated; X* [" m, g+ J6 h8 `
1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board' T6 E F$ M8 B$ U, F3 O9 H& p
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
0 t0 s W9 L5 N! ?1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol
" n( J( c& `3 j' z; a, h1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not0 f) o! t& h1 {# K& U6 ^
1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components
' p8 z5 H- u7 Z' p* O1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components
0 n S: m5 v+ W& c1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets6 y# h! q: n/ k9 f$ w
1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets3 N. G; U+ |, u$ q$ V H( K
1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF
. z4 j' x" L# ^; m: Z% S1 S0 W1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement3 P; u1 p- \6 O
1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.
3 ^, d6 D: d, f3 ` r {1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file L+ N* U7 o# @
1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.+ D* v2 r7 C8 T
1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker
! Q: a! Z& c A7 D1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates
k2 r$ e8 T7 [, e1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes
! l, B7 H( v: S2 w2 U9 }8 C% ^1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.
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发表于 2017-2-26 17:05
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发表于 2017-2-26 20:26
