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本帖最后由 紫菁 于 2017-9-14 16:05 编辑
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转 Hotfix_SPB17.20.015_wint_1of1
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! [2 r7 e* P6 @' D5 Q/ dFixed CCRs: SPB 17.2 HF015
6 e, C* t2 m- a1 W03-16-2017
, _2 \% g4 X1 g8 k6 {========================================================================================================================================================6 k. Z& P3 Q2 M9 {9 x# i
CCRID Product ProductLevel2 Title" e& v. p+ M6 A3 Q$ ~0 _6 s4 [
========================================================================================================================================================' a/ r @6 O7 H0 u7 j0 ~% J
1653366 ALLEGRO_EDITOR INTERFACES Unable to attach step model to symbol
2 s7 f6 J5 C- ^ @9 m6 s3 z( g1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model, m/ O$ R ~) y& c# T3 x
1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function9 s7 A" h5 w* @- ]6 A# I6 _
1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file# m4 w( M. b5 Z3 Q! ^. N
1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting Padstack Editor results in incorrectly scaled forms
/ X; Q. f' S+ x/ M9 P2 k8 C& G1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design1 ]. N1 F# w* a) n0 u6 |6 ]+ |
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees
: Y# K U. \ T G7 ~1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.
: P; X" ], |' B# s9 a1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously( z5 l3 l1 b) e% ~5 m0 t
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor* L" ?7 V( [- [/ q( F' @
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
* K c( C" t6 w+ Z1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used
1 X0 t" \0 X" @9 C1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places2 d6 p4 V. x( E! P1 y+ v* p
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value. w, U7 m, {9 V% @/ s, U4 m
1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically6 C9 R( n5 e7 y. ]# K0 i
1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad
! ^8 F4 A% b0 F) ]! e$ B0 m/ j g+ L' p1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout
k2 ?/ B2 Z# K8 `7 y0 q1698697 CONCEPT_HDL COPY_PROJECT Copy project corrupts the .dcf file% Q$ h/ [$ u: {, f6 [+ R' g
1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084
/ o6 C! x$ @3 o8 s2 v0 t1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position
h# q$ } Y) ^* ^3 w1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net
) F7 v7 d; N3 U3 y9 f b1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
d6 L$ k3 o. V1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation' Z5 X; r% A" E5 l
1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
, N0 R3 u7 Q( _1 _! i( {1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode8 k6 @5 Q6 z6 ~- p
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转：Hotfix_SPB17.20.014_wint_1of1.exe 链接：http://pan.baidu.com/s/1jHFB2Pg 密码：mxnk, g9 t8 `$ j0 M- V" j
Fixed CCRs: SPB 17.2 HF014/ o' o; q8 K- G6 Y$ e/ Z
========================================================================================================================================================% S! b$ b: D) t# \: y
CCRID Product ProductLevel2 Title
" m" l! {8 v5 o: l========================================================================================================================================================' M/ o" {- ?! Z5 L# `, T
1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships/ C9 E$ J& H+ u1 v' P! D. u, [
1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity$ ^* J4 O7 J3 B
1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-268
' P' ~. M8 | f- I+ m* R8 E1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data
1 ]2 A$ c1 z8 P) B! e1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data
, I7 e: U2 J: ~) A5 P1 _4 X5 Z1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors
5 u! [+ I5 B k1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.4 O$ A2 ~' r9 Q% R% s) ?
1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted* g8 D3 H. C% }3 K# a: A& u H5 R0 Y$ n
1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location
8 r$ `( A3 P0 m6 N1 O; g1685995 ALLEGRO_EDITOR SKILL All film sequence numbers are returned as 0 when using the SKILL function axlGetParam9 D6 b+ W; D5 b5 B& j
1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately# F' X, t# C- p4 F8 A" Z- M
1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6
7 `4 J: M) i. [$ }7 b1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one3 {9 o+ V' i% r" F( R* g8 {
1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled
! ^1 p4 m! G+ j- S* P$ K! A. h1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved; L: b+ T6 I# x& V: S
1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components
1 x6 ]1 j" W" s3 J1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers, L6 \* T' g9 m
1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase/ G# b y2 x& Y; a
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement2 C" K, o, f. Y2 Y8 p; F
1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message
, A" Y9 K" f, e$ q, X" g) J v1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011( f3 g& n' D1 r: v4 x! z3 ~/ `( \
1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.23 @( W3 x6 x* W k- G/ G
1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers- N5 I0 c9 x2 K1 N
1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016! c' [( Y! ^$ K8 s
1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design
* Y% s7 S; F" u( l- J1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors% ]' s& W* z. A3 Z
1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters
8 _0 I5 {' f/ p' F1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP3 g1 v! U. k- d* t
1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'* b+ Q6 N% j- [; v& R# K$ e! T$ u3 ]7 h
1705265 INSTALLATION DOWNLOAD_MGR Problem installing OrCAD Library Builder from Download Manager; u8 q- s6 y& K' W- \2 ?
1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script
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1 W, a& p9 y* a5 m( C' T bCadence OrCAD and Allegro 17.20.013 Hotfix链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv
\5 K! L) Z( g N: m# oFixed CCRs in SPB 17.2 HF013
j1 b& }. ?# i; ^0 z9 C$ C) g========================================================================================================================================================
" M; h5 E' M2 l, K" SCCRID Product ProductLevel2 Title
4 P# X! W0 l& C3 e# A========================================================================================================================================================; i1 {! Q6 N, E/ ~- L0 l8 o
1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm' f& t& m6 g1 G! x
1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer& k% J* a3 |* f6 h! d* N3 v
1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
* x2 H4 N* D) V$ m# w1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated
0 E' `/ r7 f d- Z- Y/ f5 F1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated, {( ~& I: A- N- k# {$ Q
1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board
]& E7 | L( N" x3 l1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
# b+ D, m3 l) R( n5 s1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol
4 e1 X) q( ~! o1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not' J- \$ M. @# I1 }
1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components
- c0 }; b( ?4 X! w1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components; e: K! }5 B/ x7 X: ]( n. P
1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets# ~; z- }; W$ J" r2 F% M; ^1 m
1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets
6 q9 y6 p* |" t9 W" y* s0 n0 Y% T1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF; l: y( T: V. h* f
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement9 a' t8 y ~# \
1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.
& }% @9 G) ~/ y0 F8 I, i: ?1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file/ u# r0 J- l7 V- h; t+ E5 n( n G
1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.
/ d% J7 }. i }1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker
( o1 q. i) ]+ c3 M; v; w* c1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates
3 C1 z' A: Z6 I3 b# l7 g0 R; w1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes/ x* j+ z$ x6 |; a, J
1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.
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发表于 2017-2-26 17:05
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发表于 2017-2-26 20:26
