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本帖最后由 紫菁 于 2017-9-14 16:05 编辑 }/ q* K, D: X. ?5 V
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转 Hotfix_SPB17.20.015_wint_1of1
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( Z. ^8 M# P- T2 g3 h2 GFixed CCRs: SPB 17.2 HF015
( g' h3 R7 G, D3 h% d9 O! N03-16-20170 P! ]+ K6 g+ J0 a
========================================================================================================================================================
" i$ B D* ~! Q# j/ qCCRID Product ProductLevel2 Title7 u0 ]5 b7 O" {& b6 C6 f
========================================================================================================================================================* ~9 K9 B; A: |
1653366 ALLEGRO_EDITOR INTERFACES Unable to attach step model to symbol
- O$ c' v% J4 l' x* ]1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model
" d# w; C$ T. i* n& \1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function1 t/ \6 Z \* V! {( z" N a
1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file% M5 z) H# s# h9 n& s& f# B
1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting Padstack Editor results in incorrectly scaled forms
0 A' U+ l; k( @4 y7 k: H8 l. Y5 V9 |1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design
+ B6 a8 X$ e3 B9 d1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees! I. R( D9 G0 ]6 J& L. y4 }+ n( T
1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.% O/ d/ U/ K! v
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously) W' d1 t- [: L- a; v
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
3 x' G, N) U( [2 Q* D* w" w( w/ K1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
/ _4 ^8 M) T6 X& M1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used
! O% ]' p4 `5 {1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places* W0 J9 P& R" d7 J: R
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value( [, P4 @# ^- n$ k) M) A
1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
; B, p7 [: `- \* S) H& b: d8 k& ?1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad2 T! [( |6 d6 S8 f
1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout! x. }" A$ O( Y( c* d$ `4 J. b
1698697 CONCEPT_HDL COPY_PROJECT Copy project corrupts the .dcf file
4 R; r8 _8 X9 Q+ X8 [1 Y; g4 T1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084. U8 Y0 `" C I, v/ b
1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position' w: u# y" I* l3 y
1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net
1 F4 A3 c: E' P. }2 v1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer) D+ D: F8 T# w: b. x
1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation1 g- Q# |" r0 r9 m
1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates# K6 G2 y( |# p1 z( t1 a1 j- {
1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode9 H3 v" e" R# O$ x* ^
. j0 {% ]/ _! `3 y" _2 u- ^转：Hotfix_SPB17.20.014_wint_1of1.exe 链接：http://pan.baidu.com/s/1jHFB2Pg 密码：mxnk3 G8 Z0 ], j. L) u, n' N% N+ F0 x# L4 y
Fixed CCRs: SPB 17.2 HF014. B. ]4 o9 D3 A
========================================================================================================================================================
! Y7 Z; K$ e$ n- i# }CCRID Product ProductLevel2 Title
9 O" t& Z& g4 N; O: `3 q3 i: d========================================================================================================================================================
7 a: b: {; s) G" }0 r1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships
4 a9 i% x& }# z! c8 s3 a2 Z+ k$ @1 D1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity: t8 z" }* p6 w8 y& m
1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-2683 m7 v+ h+ X# F# y$ ~
1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data1 W$ {0 a0 |1 A- b. z9 g/ ^
1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data( G5 y6 H% q0 a. {8 F$ T
1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors
8 [5 E* l" l# Q. z, z7 f! a5 _1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.
: o G1 m4 n: Q& R+ j n3 V1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted! V# N& Z; ~! G# U3 d# O" _5 ?. \
1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location& D5 Y+ R6 l6 v4 J) S o
1685995 ALLEGRO_EDITOR SKILL All film sequence numbers are returned as 0 when using the SKILL function axlGetParam
% T' d6 A% ]$ T, B3 T1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately" v- D( c* z1 D* k9 T3 B
1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6
r* O* }6 ]2 {2 }6 `' H& @1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one% w9 k0 d+ P' U) j
1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled
0 u# Q. _5 k4 i& t7 s. C) _1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved( [' j2 W, k# M8 @4 M2 o" M
1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components
0 I) N7 l0 f3 Q2 g/ g N9 I* ?1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers
7 u4 z4 b6 m9 k8 Q9 X! o1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase& g" Q# ]3 M& v \. ~' @
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement# }. B3 l- q$ M7 L6 I2 n
1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message
& U! {7 m0 i& Z D8 h1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011
; G7 {* G3 B/ C' o5 Y' Z4 _* w1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2. k! S1 v! W. t/ Q. @& ^
1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
# k( c8 i+ @7 p5 w/ P e' R1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016
! K0 O8 f0 x7 |2 N1 V a1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design
0 W+ P" c7 C% T1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors
: T# L' m0 |; f5 C+ K1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters
& |4 a# m0 n: O1 n+ p3 X/ [3 N! [6 L1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP+ b3 o ?5 H+ _% t2 g! y+ a
1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'( r" ^: |- K$ W8 O1 _9 o
1705265 INSTALLATION DOWNLOAD_MGR Problem installing OrCAD Library Builder from Download Manager
7 _9 }- x6 x, u; |1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script
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Cadence OrCAD and Allegro 17.20.013 Hotfix链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv: w' u: r6 R8 e+ {: H4 P- b
Fixed CCRs in SPB 17.2 HF0139 a+ b! [: G/ k* I' Y
========================================================================================================================================================2 q8 c" N6 ^' a9 ]& r
CCRID Product ProductLevel2 Title( \& h' P/ b' N# B
======================================================================================================================================================== b: ?2 V% J2 F$ H6 l
1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm
# ^8 D5 j# N/ H) M6 Z; `) Q1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer: }9 L. w+ w( Q) L w2 \/ i
1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
" i. b, s9 E, A2 [) p, K$ m1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated
" t) U. f; P* D% m) t0 @- z1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated* d9 Q5 }' |( o& s9 r+ r
1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board \* ^8 v0 L) i5 \; S
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor, P' y; T: f p9 b, z" S8 @
1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol
1 L6 U2 b) ^4 p) b1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
! l+ @! d! |3 p; a. u. R6 l1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components& ~ ]+ F: R. [) c" T
1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components0 y# f7 p+ T& Q% H/ C
1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets
$ u1 {" e0 O- q4 t C- ^9 O1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets
6 k- M: ?' i, s4 d Q1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF1 S& U* {" Y2 V# i0 [3 G" o
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement- ?3 V/ L) Y# C- ?, i( x- l
1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.
# U9 p5 k0 N! \4 x& H1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file
' Q+ \! t( P6 d" `1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.$ Z! {* e% o% m
1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker$ P" Z! H( S$ s
1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates: Y7 a" U% E' N7 E' G6 E& I
1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes
- S! w- x, K" u1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.
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发表于 2017-2-26 17:05
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发表于 2017-2-26 20:26
