Since the earliest days of microprocessors, system designers have been plagued by a problem in which the! _7 j8 U& \ d) K; S
speed of the CPU's operation exceeded the bandwidth of the memory subsystem to which it was connected.7 x" A! W& Z/ b7 u) t9 T
To avoid wasting CPU cycles while waiting for the memory to fetch the requested data, the universally& T9 `; f0 w+ C) ]5 Q2 H5 S
adopted solution was to use an area of faster (and thus more expensive) memory to cache main memory data." q m' [- s8 {6 N
This solution allowed the CPU to operate at its natural speed as long as the data it required was available in+ g3 W+ {9 O4 Y2 m
the cache.