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尝试画个层次原理图，很简单，就几个电阻一连，可是画完了DRC的时候总是报错：8 M; E- W9 m& F( u
Checking Misleading Tap connection4 r3 ?7 C: q2 `/ Z" v: V4 c" |
ERROR [DRC0039] Tap may not be connected with the bus Check Entire net. DD1: SCHEMATIC1, top (3.55, 2.30)1 U8 _" a) b4 \; K1 C
ERROR [DRC0039] Tap may not be connected with the bus Check Entire net. DD2: SCHEMATIC1, top (3.55, 2.30)6 B) Q3 F5 J: {
ERROR [DRC0039] Tap may not be connected with the bus Check Entire net. DD3: SCHEMATIC1, top (3.55, 2.30)& {: [( [4 c F; X6 P8 W9 X S
ERROR [DRC0039] Tap may not be connected with the bus Check Entire net. DD4: SCHEMATIC1, top (3.55, 2.30)& }; r; p: C! i- |7 j& b
hierarchical pin name  D[1..4],
! \, l* ^9 N! z1 f) M0 o Obus name DD[1..4],
6 c: A0 q. o: i6 [4 E3 j nnet alias 分别为DD1，DD2，DD3，DD4。4 V# m2 F# B: p- Z
问题出在哪呢？如果把根图上的bus name 去掉，就又报警了，& Q7 j( H1 T0 Y$ V* n2 L' e
Check Bus width mismatch, }4 a/ _) h( s
N06946 has not connected with proper width# s3 q; C/ n) ~: |' g- ~* A i+ G8 R
WARNING [DRC0030] Bus width is not matching with the port Width block1,DD[1..4]: SCHEMATIC1, top (2.45, 2.30) 3 J8 R/ q; t" `7 g* T$ f
N06946 has not connected with proper width' Z. ^" y% {3 m1 f$ n
WARNING [DRC0030] Bus width is not matching with the port Width block2,DD[1..4]: SCHEMATIC1, top (3.55, 2.30)
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发表于 2011-8-17 17:00
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