SystemVerilog for Verification

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SystemVerilog for Verification:
A Guide to Learning the Testbench Language Features
1. VERIFICATION GUIDELINES 1
& v& {3 A$ ?; @% m1.1 Introduction 1
1.2 The Verification Process 2
9 ~) L# V" i/ Q3 b5 o4 f1.3 The Verification Plan 4
; Z& O6 w- L+ P. n' h$ o1.4 The Verification Methodology Manual 4
' @0 W- b/ F7 u$ n! N: A- u/ j1.5 Basic Testbench Functionality 5
1.6 Directed Testing 5
4 f; M/ \; V2 Y. o4 L: U1.7 Methodology Basics 7
1.8 Constrained-Random Stimulus 8
1.9 What Should You Randomize? 10
, l( f  [3 f% a2 V2 b1 r+ f' w- N" b1.10 Functional Coverage 13
1.11 Testbench Components 15
8 \6 x/ ], f% ~% X9 F/ W% V; `1.12 Layered Testbench 16
1.13 Building a Layered Testbench 22
1.14 Simulation Environment Phases 23
. z8 m# a2 e( \/ _1 y& }4 g1.15 Maximum Code Reuse 24
8 E6 a- T' w* I1.16 Testbench Performance 24
1.17 Conclusion 25
- h* j/ j$ H/ ?- W* }" j/ u2. DATA TYPES 27
2 q& q& O' P8 p* @9 x2.1 Introduction 27
2.2 Built-in Data Types 27
. z# e- l4 z0 ]3 L/ iviii SystemVerilog for Verification
# i, z& g) C2 D. ~2.3 Fixed-Size Arrays 29
7 v) W, O5 u* i, Y7 y2.4 Dynamic Arrays 34
! Z) c- W5 G& Y' f/ g* E8 o7 G2.5 Queues 36
! ?, C, ~  Y" M+ b# C; Y8 f; G. F$ ]2.6 Associative Arrays 37
2.7 Linked Lists 39
! |* E/ p) Y& E" q( U+ h2.8 Array Methods 40
" }: l% O7 j+ F' e( ]2.9 Choosing a Storage Type 42
2.10 Creating New Types with typedef 45
2.11 Creating User-Defined Structures 46
2.12 Enumerated Types 47
6 ]1 Z* }& g$ J* I7 `6 ?2.13 Constants 51
2.14 Strings 51
2.15 Expression Width 52
2.16 Net Types 53
2.17 Conclusion 53
3. PROCEDURAL STATEMENTS AND ROUTINES 55
3.1 Introduction 55
3.2 Procedural Statements 55
8 q! [/ s& y( y& L3 q3.3 Tasks, Functions, and Void Functions 56
# k( O1 Y; ^1 v# o  Z8 Z; L3 x3.4 Task and Function Overview 57
3.5 Routine Arguments 57
! Q4 H+ d2 V- \! J: V0 }! |3.6 Returning from a Routine 62
3.7 Local Data Storage 62
% e! g. {5 t" Y3.8 Time Values 64
3.9 Conclusion 65
+ [. H8 d5 a' E, C0 M7 h4. BASIC OOP 67
4.1 Introduction 67
4.2 Think of Nouns, not Verbs 67
; l9 H* b- l& t0 g/ u4.3 Your First Class 68
0 Q+ e8 w. Q" g6 @2 @' B4.4 Where to Define a Class 69
4.5 OOP Terminology 69
+ G( h1 F4 H% p* m4 }8 T) u4.6 Creating New Objects 70
/ q# F% T% \! \4.7 Object Deallocation 74
4.8 Using Objects 76
1 l2 Z5 k  x1 L1 h: @3 A& I) G" I$ L9 l9 B4.9 Static Variables vs. Global Variables 76
  R2 f2 C% l: v/ J$ {  s4.10 Class Routines 78
  c* z- l% p. [# X7 _7 S4.11 Defining Routines Outside of the Class 79
# ]& A5 q% h% g1 c4.12 Scoping Rules 81
: r# T( P  A+ q4.13 Using One Class Inside Another 85
6 @. V  A& ^; d  g: Y& O; _  }4.14 Understanding Dynamic Objects 87
4.15 Copying Objects 91
4.16 Public vs. Private 95
Contents ix
4.17 Straying Off Course 96
- q6 q9 D0 T( M4.18 Building a Testbench 96
& C. X$ l+ |; _6 I8 P8 t) K6 l4.19 Conclusion 97
5. CONNECTING THE TESTBENCH AND DESIGN 99
5.1 Introduction 99
5.2 Separating the Testbench and Design 99
% ]3 y1 t3 V& X% a( H( f! v; L, u5.3 The Interface Construct 102
9 y8 `: m9 h- N4 k1 e; l5.4 Stimulus Timing 108
5.5 Interface Driving and Sampling 114
* O, u- s. y0 ^# {4 K- M5.6 Connecting It All Together 121
2 M! x8 _* M2 D) v, F9 M5.7 Top-Level Scope 121
/ v+ G* s4 [8 k7 I" J  t5.8 Program – Module Interactions 123
: N, m! M, w% L  B/ U5.9 SystemVerilog Assertions 124
, @4 E7 x0 ?3 C8 ^5.10 The Four-Port ATM Router 126
5.11 Conclusion 134
( o0 y5 ?0 p% B3 n* V6. RANDOMIZATION 135
6 e. r- Z2 L/ t4 l- b9 R5 e  V" @+ X6.1 Introduction 135
6.2 What to Randomize 136
6.3 Randomization in SystemVerilog 138
6.4 Constraint Details 141
9 q9 [; {0 s2 _) u/ w1 U6.5 Solution Probabilities 149
3 r/ l' r+ [5 h5 a; n6 {0 [6.6 Controlling Multiple Constraint Blocks 154
0 r* Q/ j8 n5 _" @& A6.7 Valid Constraints 154
6.8 In-line Constraints 155
6.9 The pre_randomize and post_randomize Functions 156
1 R9 x% `* K* s) d2 l3 y6.10 Constraints Tips and Techniques 158
* c( }5 a( f; E2 Q6.11 Common Randomization Problems 164
6.12 Iterative and Array Constraints 165
6.13 Atomic Stimulus Generation vs. Scenario Generation 172
6.14 Random Control 175
& l: `+ ?) N: Z5 d6.15 Random Generators 177
6.16 Random Device Configuration 180
# S! o2 I3 F& L0 |6.17 Conclusion 182
7. THREADS AND INTERPROCESS COMMUNICATION 183
( L: o% I* f) ~7.1 Introduction 183
7.2 Working with Threads 184
7.3 Interprocess Communication 194
7.4 Events 195
7.5 Semaphores 199
2 A/ g" l8 x- g' j/ F: F4 K8 o( M7.6 Mailboxes 201
- I/ A5 H% e% u: x4 L- G) H7.7 Building a Testbench with Threads and IPC 210
x SystemVerilog for Verification
# i$ q$ J! z7 s+ K8 p2 Q$ p6 I7.8 Conclusion 214
& y& m6 Y2 f6 N7 r5 U" q8. ADVANCED OOP AND GUIDELINES 215
8.1 Introduction 215
8.2 Introduction to Inheritance 216
8.3 Factory Patterns 221
8.4 Type Casting and Virtual Methods 225
5 j2 g& q+ I1 T3 K0 y4 a+ _! {8.5 Composition, Inheritance, and Alternatives 228
8.6 Copying an Object 233
* v& m5 |' j+ \; a' k8.7 Callbacks 236
8.8 Conclusion 240
& Q: g! P1 J0 G8 t9. FUNCTIONAL COVERAGE 241
: e4 s; _8 E& z, V9.1 Introduction 241
  S+ H9 \5 i* z& c8 z9.2 Coverage Types 243
6 q$ H& [4 N% _2 r9.3 Functional Coverage Strategies 246
8 o& @# E6 \- e  Z8 v* v9.4 Simple Functional Coverage Example 248
9.5 Anatomy of a Cover Group 251
8 h# H$ {4 u9 @( W1 n9.6 Triggering a Cover Group 253
9.7 Data Sampling 256
- O1 [" y" F( D& P4 `0 N  i, l9.8 Cross Coverage 265
9.9 Coverage Options 272
9.10 Parameterized Cover Groups 274
7 g$ L6 k% G2 k9.11 Analyzing Coverage Data 275
+ G* ~3 n6 i0 {5 E+ P# X- K2 N9.12 Measuring Coverage Statistics During Simulation 276
( L  t- x9 G9 W6 A9 Z9.13 Conclusion 277
& W6 A) n- J; u- C10. ADVANCED INTERFACES 279
10.1 Introduction 279
10.2 Virtual Interfaces with the ATM Router 279
0 q0 k! ?. W8 o10.3 Connecting to Multiple Design Configurations 284
10.4 Procedural Code in an Interface 290
& @* o+ y, p  Y4 u: X10.5 Conclusion 294
References 295
- |- ~) S& `" J% q: \) ^* K" mIndex 297

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