SystemVerilog for Verification

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SystemVerilog for Verification:
/ `; g* N5 j: @: M  |  dA Guide to Learning the Testbench Language Features
6 A/ S/ t: ]3 `6 W' N$ w1. VERIFICATION GUIDELINES 1
1.1 Introduction 1
1.2 The Verification Process 2
1.3 The Verification Plan 4
  u9 t, v7 U; s8 s1.4 The Verification Methodology Manual 4
" b2 c/ M) O6 n; p# G+ J1.5 Basic Testbench Functionality 5
; F2 P7 [8 k( |$ G( d1.6 Directed Testing 5
0 q% {9 H$ M  p/ S& c* A1.7 Methodology Basics 7
1.8 Constrained-Random Stimulus 8
$ x+ D8 }6 @  w" H: L4 K1.9 What Should You Randomize? 10
1.10 Functional Coverage 13
1.11 Testbench Components 15
1.12 Layered Testbench 16
) g  {- P7 C& m  {% ~1 Y5 _1.13 Building a Layered Testbench 22
+ W5 v& Z+ B! |7 Q1.14 Simulation Environment Phases 23
1.15 Maximum Code Reuse 24
1.16 Testbench Performance 24
1.17 Conclusion 25
2. DATA TYPES 27
2.1 Introduction 27
- C- S# ~8 @: R, |3 l2.2 Built-in Data Types 27
1 s0 V- x0 e; Z' u: Q# Sviii SystemVerilog for Verification
2.3 Fixed-Size Arrays 29
2.4 Dynamic Arrays 34
( I4 L1 H. l9 j) L* }* s" J2.5 Queues 36
2.6 Associative Arrays 37
$ h2 C+ H7 O+ q% }/ C0 ~  l& J7 R2.7 Linked Lists 39
5 x0 a1 W  R( f4 L4 M1 `: g2.8 Array Methods 40
+ L& z$ q/ [9 l6 V% z8 B% C2.9 Choosing a Storage Type 42
9 F- Y4 m$ D' Q6 i0 }% P2.10 Creating New Types with typedef 45
2.11 Creating User-Defined Structures 46
( _: ?6 ^1 ]) r2.12 Enumerated Types 47
5 }$ P' V3 ^' f* k; S7 Z' e2.13 Constants 51
  z0 b: ~2 S. B3 g! h/ ^2.14 Strings 51
3 s4 k5 `# Q  K1 d+ P8 ^8 f" \; {. B2.15 Expression Width 52
2.16 Net Types 53
2.17 Conclusion 53
3. PROCEDURAL STATEMENTS AND ROUTINES 55
3.1 Introduction 55
2 Q) K' ~6 o& o0 {9 X4 ^1 `3.2 Procedural Statements 55
3.3 Tasks, Functions, and Void Functions 56
3.4 Task and Function Overview 57
3.5 Routine Arguments 57
3.6 Returning from a Routine 62
4 r) h2 [8 ?% V7 L& u3.7 Local Data Storage 62
7 M3 @. ^7 g, ^. P+ i( S5 l3.8 Time Values 64
3.9 Conclusion 65
4. BASIC OOP 67
  k, T, F3 j/ v9 F' C3 r; l& u4.1 Introduction 67
4.2 Think of Nouns, not Verbs 67
4.3 Your First Class 68
" |* V6 p9 B3 ^. c$ f/ {0 n4.4 Where to Define a Class 69
% ^4 Q" ?1 t( z0 y/ }4.5 OOP Terminology 69
/ k0 I6 D1 ~2 s( Z7 v4.6 Creating New Objects 70
6 L2 L4 o& m! f$ E9 P/ J4.7 Object Deallocation 74
# d: K7 n1 ^; B* o- H4.8 Using Objects 76
4.9 Static Variables vs. Global Variables 76
4.10 Class Routines 78
7 u2 W& u& d+ H$ M* C# z( q4.11 Defining Routines Outside of the Class 79
- Y7 r4 X1 D# P: ~  Y9 E9 P, a4.12 Scoping Rules 81
6 \5 s2 J6 q% R/ |- K( ]# K( a4.13 Using One Class Inside Another 85
6 i: N+ c1 d" F. \) v4.14 Understanding Dynamic Objects 87
0 G# a+ \! N  P* P& Y6 f. o4.15 Copying Objects 91
4.16 Public vs. Private 95
3 R& S- v; T9 iContents ix
4.17 Straying Off Course 96
; ~+ B" C. e; N( \7 E8 [4.18 Building a Testbench 96
1 ^- ^8 W2 j0 J" O0 e4.19 Conclusion 97
5. CONNECTING THE TESTBENCH AND DESIGN 99
2 W& @( y# E7 t. ]: e% X; f5.1 Introduction 99
5.2 Separating the Testbench and Design 99
4 F+ Q3 K0 W: B- ~5.3 The Interface Construct 102
5.4 Stimulus Timing 108
5.5 Interface Driving and Sampling 114
* d8 Y: D# D, w5 N( v5.6 Connecting It All Together 121
6 S# \4 s$ {) s9 Q5.7 Top-Level Scope 121
5.8 Program – Module Interactions 123
5.9 SystemVerilog Assertions 124
5.10 The Four-Port ATM Router 126
5.11 Conclusion 134
& @  m+ b  N% E3 d+ X% K) F6. RANDOMIZATION 135
6.1 Introduction 135
% t. v/ [4 W. @6.2 What to Randomize 136
2 O' u1 R9 B, @6.3 Randomization in SystemVerilog 138
6.4 Constraint Details 141
' u& o  _4 G* B; ]# A8 d6.5 Solution Probabilities 149
6.6 Controlling Multiple Constraint Blocks 154
7 C! t. D! q, R8 J& N9 }3 n6.7 Valid Constraints 154
- q4 F5 m! G# J9 W$ E3 Y( R. k6.8 In-line Constraints 155
6.9 The pre_randomize and post_randomize Functions 156
& T  w# i: |& R  ~2 f6.10 Constraints Tips and Techniques 158
' p" c5 D( N2 z7 `7 e' I( i; S6.11 Common Randomization Problems 164
5 u" L- {2 R6 \$ B) k$ y6.12 Iterative and Array Constraints 165
6.13 Atomic Stimulus Generation vs. Scenario Generation 172
6.14 Random Control 175
6.15 Random Generators 177
6.16 Random Device Configuration 180
6.17 Conclusion 182
7. THREADS AND INTERPROCESS COMMUNICATION 183
7.1 Introduction 183
7.2 Working with Threads 184
7.3 Interprocess Communication 194
5 k' Y( J8 a: H, K7 Y* V4 y/ `7.4 Events 195
: g( @; z) y" L8 F7.5 Semaphores 199
& Z4 a2 T4 `$ B+ n  V7.6 Mailboxes 201
7.7 Building a Testbench with Threads and IPC 210
7 U- Z2 p+ U1 H3 y& Gx SystemVerilog for Verification
7.8 Conclusion 214
8. ADVANCED OOP AND GUIDELINES 215
, P/ d" H# X: c; _9 g; J, G8.1 Introduction 215
8.2 Introduction to Inheritance 216
% S( a9 k! M/ H" Q: z+ t" r8.3 Factory Patterns 221
8.4 Type Casting and Virtual Methods 225
8.5 Composition, Inheritance, and Alternatives 228
8.6 Copying an Object 233
7 Z% C7 M* N% G9 N; v8.7 Callbacks 236
8.8 Conclusion 240
6 M+ U7 N* ]3 D  G+ v9. FUNCTIONAL COVERAGE 241
9.1 Introduction 241
0 W8 a/ R; ?2 C: E5 M9.2 Coverage Types 243
9.3 Functional Coverage Strategies 246
4 k' r) }6 h. ?& J9.4 Simple Functional Coverage Example 248
/ S$ r" R: I5 P. `0 f8 n& s9.5 Anatomy of a Cover Group 251
1 S2 C. r+ h2 q  n9.6 Triggering a Cover Group 253
9.7 Data Sampling 256
9.8 Cross Coverage 265
9.9 Coverage Options 272
9.10 Parameterized Cover Groups 274
9.11 Analyzing Coverage Data 275
( E, j0 J- {+ g8 I! A; }9.12 Measuring Coverage Statistics During Simulation 276
9.13 Conclusion 277
10. ADVANCED INTERFACES 279
10.1 Introduction 279
1 C/ z  U0 ]  h7 v10.2 Virtual Interfaces with the ATM Router 279
10.3 Connecting to Multiple Design Configurations 284
+ g! j/ f# H, b/ e- G& W4 S8 a10.4 Procedural Code in an Interface 290
( ^# j3 v0 `9 _3 m8 x- {+ H4 M10.5 Conclusion 294
References 295
+ P* r4 n% X% s/ Q0 Y$ eIndex 297

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