Pkg Warpage & Assembly Challenges Using Thin Core Substrate

admin · 发表于 2019-9-27 15:51

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Author: Ajit Dubey,NetLogic Microsystems

Abstract
The need for thin core substrates is increasing in the industry to meet low inductance.
However, there are major challenges of reducing thin core substrate warpage in assembly which needs thorough understanding of the assembly process steps and its effect on warpage.
There are various assembly stages that influence the package warpage as a result of time and temperature. Reflow process during die attach, underfill curing and lid attach process play a significant role in package warpage.
Substrate manufacturers typically provide substrate warpage of 4mils max which does not allow much margin left in assembly considering the number of reflows and curing profiles the package undergoes during assembly.
This paper illustrates the warpage at each assembly process step and its impact on assembly yield and reliability with 400um thin core 27x27mm, 4-2-4 package.
In this paper, package warpage at various reflow profiles, underfill curing profiles and lid attach processes has been evaluated.
The warpage studies are carried out on a flip chip organic BGA package with underfill and a single piece lid using a 400um thin core substrate. The package also comprises of low k layers which is another challenge that is explored to ensure the reliability of low k delaminations on a thin core substrate. The challenges are increased further since the package also needs to qualify board level reliability in addition to level 1 qualification.

The paper also illustrates the board level reliability tests and its qualification results.

I. Introduction
Thin core substrates significantly help to provide better electrical performance by lowering inductance. This also helps in providing higher routing density.
Flip Chip assembly process has been optimized over the years to achieve greater than 99.5% assembly yield. The challenge is now to achieve the same yield using thin core substrates. The challenges further increase with the requirements of 90nm node, low K dielectric layers, and large die sizes. Low K dielectric materials are used to enhance electrical performance. To lower the inductance value the low K materials are made more porous. As a result the mechanical strength is considerably reduced as compared to FSG dielectric material. Large die sizes also contribute to warpage.
The package also comprises of tighter design rules and shrinks in bump size and bump pitch. The bump pitch is shrunk from 225um to 200um for 130nm node technology. For the current package the bump pitch is further shrunk from 200um to 180um for 90nm node technology. The bump height is also reduced from 100um to 85um. The substrate core thickness is reduced to 400um in comparison to the widely standard thickness of 800um. Increasing the porosity of low K dielectric material, shrinking the bump pitch, reducing the bump height and reducing the core thickness there by increasing the package warpage weakens the solder joint to withstand the stress during fatigue life tests. The material characteristics of low k layers, bump geometry,substrate build up materials, substrate flip chip pad geometry,flux for die attach, coefficient of thermal expansion are all critical factors to reduce stress at each interface layer. Proper selection of underfill and the underfill assembly process is very important for the success of a reliable package. Underfill protects the bumps at each interface namely, under bump metallurgy passivation and at substrate solder resist interface. Underfill delamination jeopardy exists at various interfaces, and is driven by the shear and peeling interfacial stresses which are directly affected by underfill fillet geometry. Delamination is also dependent on interfacial adhesion. Reducing the package warpage will help in lowering the risk of interfacial delamination. This will improve the interfacial adhesion by reducing the interfacial stresses. In addition to proper selection of materials, assembly process tools and process conditions also play a significant role in the reducing the warpage of the package. Improper process conditions of time and temperature would lead to increase in package warpage causing die cracks, underfill cracks and solder joint cracks.
II. Approach
Following package details specific to customer’s foot print layout was designed.
Shipping trays:
Two types of shipping trays for Substrates were considered. One is low cost tray with large array and other is a more sturdy with less array 4x10 is used.
Test chip:
The test chip consists of 8 layers of Cu interconnection and one layer of Al with silicon nitride passivation. The test chip size is 19.92x 18.8mm. The bump composition is eutectic. Bump pitch is 225um and total number of bumps are 6807. Test chip thickness is 31mils and is not back grinded. The UBM diameter is 108um.
Substrate:
Substrate warpage is measured during incoming inspection. The warpage at incoming is controlled at 4mils maximum.
The warpage is measured by a profiler along the diagonal of the substrate. The tool used in this case is an automated warpage measurement tool. The warpage is measured by a laser pointer. The measurement is done by point to point. The distance between each point is 1mm. The diameter of the laser pointer is 200um.

Fig 1: Schematic Picture of the substrate with points/line of measurements.

Substrate/Package:
The substrate size is 27x27mm with 4-2-4 build up structure and 400um core thickness. The flip chip pad diameter is 145um and flip chip solder resist opening is 105um. The flip chip solder composition is eutectic 63Sn/37Pb. The BGA pad surface finish is SOP (solder on pad) and the solder sphere are also eutectic 63Sn/37Pb. The BGA pitch is 1mm with BGA I/O of 576. The total substrate thickness is 0.89 nominal.The package comprises of the flip chip die and heat spreader. The heat spreader is a single piece with no stiffener. The material composition is Nickel plated Copper. Substrate is baked to ensure moisture is removed before flip chip attach process.

Test Chip attach:

Singulated test chip is then assembled using a no clean flux and with a eutectic reflow profile of 230C peak temperature.
Underfill process:
Piror to underfill process the parts are baked at 150C for 2 hours to ensure moisture is driven out before underfill dispense.
Two types of underfills were selected with different Tg and modulus and curing temperatures to study the impact of warpage with different curing conditions. The curing conditions are in the range from 150C to 160C for 1 hour.
Lid attach:
Lid is Nickel plated Cu. Lid attach process is done by dispensing a thermal interface material between the die and dispensing lid adhesive material along the edges of the substrate to attach the lid. The package is the cured in an oven for 150C for 1 hour.

BGA attach:
Eutectic bumps 63Sn/37Pb are used with ball diameter of 0.6mm. No clean flux is used with BGA reflow using eutectic reflow profile.

Fig 2: Flip Chip Assembly Process Flow

Ⅲ. Effect of warpage and assembly challenges

Wafer dicing:
Wafer dicing is done using a two step cut process. Die is designed with a seal ring that ensures there are no microcracks that propagate in the active area of the die or near the bumps.
Test Chip attach and reflow:

Thin core substrates are prune to warpage at any process where temperature with respect to time plays a role. All fixtures used for handling the substrates should be sturdy in order to avoid any warpage. Yield loss for bumps getting shorted to each other are often seen after chip attach reflow.The bump shorts are often seen at the corners of the die.
This is because the substrate gets warped during reflow as an effect of temperature with respect to time. As a result bare substrates with known warpage were evaluated. Two types of substrates warpage range were considered. Sample size of 24 units for 0-4mils and 96 units for 4-6mils were considered.
Fig 3 shows that the bumps shorts are higher than non wets for substrates with 4 to 6 mils warpage.

Figure 3: Effect of warpage at die attach reflow

Figure 4: Bump shorts and non wet locations on the die

Location1: Detect 5 units bump bridge and 4 units non wet.
Location2: Detect 2 units bump bridge.
Location3: Detect 1 units bump bridge.
Location4: No abnormal finding

Figure 5: Warpage after die attach on units with bare substratewarpage of 4-6mils

The data shows that bare substrates over 4 mils warpage has high a risk of non-wet and bump bridge due to severe warpage variation after die attach reflow. As a result optimization of reflow profile and effect of flux process was evaluated to verify if warpage can be controlled at die attach reflow process. Fig 4 , 5 and 6 show the location of warpage and the bump shorts at the die corners.

Figure 6: X-Ray image shows bump bridge at location 1

The objective is to evaluate if low peak temperature in relation to flux process can help to maintain or reduce the warpage.
Two flux processes namely dip type and flux jetting was used for evaluation in conjunction with two types of reflow profiles with 215C and 230C peak temperatures. Sample size of 20 units was considered for each leg.

Figure 7: Coplanarity trend with different reflow profile peak temperature with two types of flux processes (dip flux and jet flux)

Dip flux with reflow profile of peak temperature 230C showed one unit with bump non-wet. The data shows that the substrate warpage increased significantly with higher peak temperature. This resulted in corner bumps causing opens.

Figure 8: X-Ray image of corner bumps with non wets

Warpage after each process step is also evaluated with known bare substrate warpage.

Fig 9: Warpage after each process and different underfill cure profiles

It is seen from Fig 9 that warpage increases after die attach and underfill process. The warpage gap is lower using clip attach process during lid curing.
In order to understand the difference between the package of 400um core thickness and 800um core thickness, a package close to the test vehicle package was considered to compare the coplanarity trend at die attach process. Two reflow profiles were considered with leak temperatures of 215C and 230C.
The 800um core thickness package size is 31x31mm with die size of 17.5x18.24mm. The package structure is 4-2-4 same as the test vehicle package. The package also comprise of a single piece heat spreader.

The data shows that the warpage of the package is higher at 230C reflow peak temperature than 215C for 400um core thickness package. To reduce the warpage two proceses were evaluated before and during die attach reflow. The data shows that the warpage is higher in thin core package although the package size is larger (31x31mm) with 800um substrate core thickness than the test vehicle package (27x27mm). This is seen in Fig 11 with die and Fig 12 with raw substrate.
In order to reduce the warpage on thin core package, innovative process changes and tools needs to be evaluated to establish a robust assembly manufacturing process. The key to achieve the process is to have some process and tool to keep the package flat during reflow and cure process. This can be done through developing new assembly tools and optimizing reflow profiles.

Fig 10: Warpage comparison of thin & thick core package at different reflow profiles

Fig 11: Warpage comparison of thin & thick core package at 230C peak reflow temperature

Fig 12: Warpage comparison of thin & thick core substrate without die at 230C peak reflow temperature

Pre-attach stiffener:
A pre-attach stiffener on the substrate was considered. A stiffener ring would be pre attached at the substrate manufacturing site.
Top cover plate:
Another process used was top cover plates on the carrier boat restricting the movement of the substrate during die attach reflow. The top cover plate shown in Fig 13 is mounted on the carrier boat carrying the substrates all throughout the assembly process. Currently the substrates sit freely in the pockets of the carrier boat. The top cover plate is placed on the boat. This top cover plate restricts the movement of the substrate in the pockets of the carrier boat.

Fig 13: Top cover plate

Fig 14: Warpage comparison of pre-stiffener attach, standard control process and with top cover plate

It is seen from the charts that warpage is increased after chip attach and after underfill process. However, after lid attach process warpage is reduced in comparison after underfill process for all legs. In case of leg#1, there is no lid as this is with pre attached stiffener. The chart shows there was no significant difference in warpage reduction with stiffener and with top cover plate in comparison to standard process. However, the standard process had 1 fail of bump bridge and 0 fails with pre stiffener and top cover plate process. This indicates that the pre stiffener attach and top cover plate process may help in reducing the warpage and there by reduce non wet bumps. Pre-stiffener attach process may prove expensive as this needs to be assembled at substrate manufacturing site. The approach of top cover plate is more practical and cost effective as the same top cover plates can be used for high volume manufacturing process.
To have a further clear understanding, warpage evaluation was by comparing parts using normal production where units are freely sitting in the pockets of the boat and parts fixed in a carrier boat by means of top cover plate.
A 400um core thickness substrate was used with size of 27x27mm and test chip size of 20x20mm. The substrates initial warpage was grouped into two sets. One set was in the range of 0 to4mils and another was 4 to 6mils. It is seen from previous experiments that the two critical areas of warpage are die attach process and underfill process. Warpage data was collected after each process such as substrate bake, die attach, underfill, lid attach and ball attach process. The below charts represent warpage after die attach and underfill process since the effect of warpage is seen after these processes.

Fig 15: Warpage of 400um core package with substrate <4milswarpage after each process

Fig 16: Warpage of 400um core package with substrate 4 to 6 milswarpage after each process

The data from Fig 15 and 16 shows, for bare substrates between 0 to 4 mils there is no significant difference in warpage at both processes, after die attach and after underfill process with current production carrier boats and units fixed in carrier boats. For substrates between 4 to 6mils there is no significant difference in die attach. However, after underfill process the warpage is higher for units in current production carrier boats than units fixed in carrier boats using the top cover plate. This is a first set of data collected and a larger set of data needs to be collected to re-confirm the results.
Below charts Fig 17 and 18 represents warpage gap before and after substrate pre-bake and warpage gap after substrate pre-bake and after chip attach process. The chart shows that warpage gap is higher after pre-bake and chip attach process for both types of substrates.

Fig 17: Package warpage gap with bare substrate <4mils

Fig 18: Package warpage gap with bare substrate 4 to 6 mils

Underfill process:
Two different underfills were also evaluated with different curing profiles. There was no significant difference in waprage between the two underfill curing profiles.
Lid attach process:
Only one type of thermal interface material was considered and also one type of lid attach clamping was considered. It is seen from previous experiment that lid attached parts that are clipped shows reduced warpage than those that are not clipped.
Ball Attach process:
The same production reflow profile was used and no change in reflow profile was evaluated.
Hard tray and soft tray:
It is recommended substrate supplier ships substrates in hard trays rather than in soft trays particularly for substrates with thin core thickness. Studies show that substrates tend to warp in thin plastic tays with large array than in standard jedec trays.
IV: Reliability Results
Level I: Following reliability tests were performed.
Moisture sensitivity level 4 (MSL 4) and temperature cycling -55/+125C , 1000 cycles.
MSL4 + MSL4+HAST, 96hrs @130C, 85%RH, biased MSL4+THB, 1000hr @85C, 85%RH, biased HTOL 1000 hrs.
All units passed all the above reliability tests and no underfill delamination or low K cracks observed in any of the tests. Level II: Following tests were conducted: Temperature cycling 0/+100, 3500 cycles using a daisy chain board, daisy chain die and daisy chain substrate. Shock and bend test as per Jedec/ IPC test method 9702.
All units passed TC0/+100, 3500 cycles and met the customers requirements of shock and bend tests.
V: Conclusion
Based on the test vehicle and process conditions it is recommended to maintain the substrate warpage below 4 mils to avoid bump non wets and package interface delaminations. These challenges will further increase as we progress with fine bump pitch, thin core substrates and silicon technology of 45nm node and below. Parts that are clamped in carrier boats with no movement and clipped for lid attach process have reduced warpage than parts freely placed in carrier boats without clip attach during lid attach process.

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