Basics of chip/package codesign in a large flipchip application

admin · 发表于 2019-9-27 15:51

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The value of chip-package codesign is well established. Complex parts with high-speed signals put more constraints on the design of both IC and package, and careful design is required to achieve performance while maintaining manufacturability and controlling cost. For example, through codesign it is possible to package quite complex ICs in low-cost plastic ball grid arrays (PBGAs). Codesign is an absolute requirement for the effective design of large flip-chip ICs and their associated packages.

The decision to use flip-chip
Often the choice between wirebond and flipchip for a specific part is not clear. In general, the characteristics listed below indicate a need for flipchip. How many of these characteristics exist for a specific IC, and to what degree, indicates how strongly the part needs flipchip.

1. A large number of signals

2. A large number of power and ground connections

3. High power dissipation, typically greater than a few watts

4. High-signal speeds and significant signal-quality requirements

A design example
We will use as an example a communications ASIC, approximately 15 x 12 mm, with 530 signals. Many signals are high-speed differential pairs, with a data rate in excess of 4 Gbps. Power dissipation is estimated at 25 watts. The combination of high power dissipation, many high-speed signals, and total signal count clearly determine the need for flip-chip.

The desired package is a 35 x 35 mm BGA with 1155 balls on 1.0 mm pitch. It is also desired to limit the package substrate to eight layers in order to control the cost. Figure 1 shows a typical cross-section of the package substrate metal layers.

Figure 1: Cross-section of build-up substrate

The IC is at the top, and the PC board is at the bottom. This is a "build-up" substrate, with three thin, high-density layers built on each side of a thick, low-density core.

Areas of concern
The design problem can be divided into several main areas which can initially be handled independently. As the design comes together, of course, interactions between these areas must be considered. A typical division might be as follows.

1. The core power and ground supply interconnect
2. The signal, power, and ground paths for high-speed differential signals
3. The signal, power, and ground paths for high speed parallel interfaces. (DDR, for instance)

In most cases these areas will be located in different part of the IC, with locations determined by the IC floorplan and system requirements.

Core Power and Ground
The core power/ground distribution is very important and should be defined first. To control the noise generated in the power/ground interconnect, the impedance of the path through the package must be minimized. In general, the path should be as short as possible, consist of many parallel paths, and maximize the coupling between Vdd and Vss.

The following design ideas may be used to achieve the best possible connection from the chip into the package.

1. On the IC, bumps should be placed to match with the on-chip power and ground grids

2. The area used for these bumps should be expanded to fill the available space.

3. The bump pitch should be large enough to assure that the substrate power and ground planes below them will remain continuous, even though there are a large number of vias passing through. This is very important! It is generally OK for the core power/ground bumps to be on a different pitch than the signal bumps

4. Maximize the coupling between Vdd and ground, usually by alternating bump assignments.

In the example part, a total of 2200 bumps were used for the core power and ground connections. Note that there is generally no cost penalty for using more bumps, as long as the bump pitch is within the design rules. Figure 2 shows the bump pattern.

Figure 2: Bump Pattern

This is often a useful bump arrangement, where the signals and their associated power and ground are located at the edge of the IC, and the bumps for the core power and ground fill the center area.

Similarly on the BGA substrate, we need to keep the impedance as low as possible. The same ideas apply: short paths, many parallel paths, and maximum coupling between Vdd and ground In the BGA, the following things can be done.

1. Assign power and ground balls directly under the IC.

2. In many parts, core ground is made common with [url=]I/O[/url] ground. This gives more parallel current paths.

3. Use several layers as full-size ground and power planes, allowing better spreading of currents into the multiple paths.

4. Connect each power or ground ball directly with all of its associated planes.

5. Connect each power or ground bump directly with all of its associated planes.

Figure 3 shows a cross-section of the core area of a substrate where these guidelines are applied. Note that the upper and lower build-up vias are directly in line with their bumps or balls.

Figure 3: Core power/ground connections

The core vias may be offset slightly because of manufacturing design rules, but should be placed one per ball. In the example design, 109 bumps were used for Vdd and 318 for ground. This gave an inductance of the final core power/ground interconnect of just a few picohenries.

A SERDES example
Many advanced ICs contain some number of high-speed I/O signals, often serializer-deserializers (SERDES) with differential signals. Data rates in excess of 4 Gbps are not uncommon. These signals will require close attention to guarantee good performance, and should be considered after good power distribution has been assured.

Often, with special high-speed I/O, the bumps are part of the IO cell, so the pattern and assignment is fixed. Figure 4 shows an example bump arrangement for a single cell. SERDES I/Os typically require connections for the two signals and for several reference and supply voltages. The I/O block, and so the bump pattern, is repeated as necessary.

Figure 4: SERDES bump pattern

Layer Assignment
Both the bump assignment and signal-quality considerations should drive the assignment of the layers in the substrate. Given the bump arrangement shown, it efficient to connect the outermost bumps (Vdd) to a plane on the surface. The next inner bump row can be connected on the next lower layer, and so on. Using the layers in this way helps avoid vias that would block the space needed for escape from inner bump rows. In this case the bump order allows a layer order assignment that will also give good signal quality. Figure 5 show a layer assignment that works well with this bump configuration.

Figure 5: SERDES Layer usage

Note that the signal paths are configured here as stripline, with ground planes above and below. This arrangement is generally the best choice for high-speed signals, because it gives the good control over their characteristics. The various reference voltages (VDD, GND, and VTT) are carried by planes that fill the area from the IC to the edge of the package. The IC bumps connect directly to their associated planes.

BGA ball assignment
Assignment of the BGA balls for this kind of signal must consider both the requirements of the package and of the application PC board. Routability and signal quality must be maintained in both. In all cases, the plus and minus signals of each differential pair should be kept together. Separating these pairs from each other by reference voltages balls will give some isolation between the signals, and provide good continuity for the signal return paths and the reference voltages, Figure 6.

Figure 6: SERDES Ball Usage

Signal routing
Signal-line dimensions of width and space must be chosen to achieve the specified differential impedance and tolerance while keeping within the limits of manufacturing. The dimensions must also allow sufficient routability in the substrate. Substrate manufacturer's recommendations are very useful here, because they can consider their manufacturing tolerances and effects such as non-rectangular line cross-sections. In the example part, line width was 27 microns, and the space was 47 microns. Figure 7 demonstrates "good" signal routing for these differential signals.

Figure 7: SERDES signal paths

Lengths have been controlled to align the arrival times of the plus and minus signals of each pair. Suitable space must be maintained between pairs to control coupling. In this case, a space of 100 microns (3x the distance from the trace to the ground planes) guaranteed that the coupling between pairs was less than 4%. The electrical performance of an interconnect like this should be checked by simulation. Figure 8 shows typical results of such simulation, indicating good performance

Figure 81: Cross-section of build-up substrate

DDR Example
A high-speed parallel bus, such as a double data rate (DDR) memory interface, requires a different approach because the speeds are lower but the number of signals involved is much larger. The design of such a bus requires a lot of interaction between the functions of I/O placement, redistribution layer (RDL) design, bump placement and assignment, substrate routing, and ball assignment.

Following an initial placement of the peripheral I/O cells and initial assignment of the BGA balls, the design problem becomes one of placing and assigning the bumps such that both the redistribution (from I/O cell to bump) and the substrate routing (from bump to ball) can be achieved with acceptable characteristics. Important constraints on the RDL design include line width and space, dc resistance of the paths (some will be carrying relatively large currents), and current density (to control electromigration). In the substrate routing, the design is constrained by the available line width and space, the need to escape from the high-density bump area, the desired characteristic impedance, delay (length) differences between signals, and controlling crosstalk between signals.

Often many of the RDL paths will have constraints on minimum width and maximum length, to limit electromigration and dc resistance. This can cause the available routing space to fill up very quickly, and I/O-to-bump assignments will be determined by the available routing space in the RDL. It may be necessary to update several times with the I/O designer, modifying the I/O placement and bump assignment as the design progresses. Figure 9 shows a small portion of an example RDL layer design.

Figure 9: Example of redistribution routing

In a fast bus, it is necessary to provide enough power and ground balls placed among the signal balls to control simultaneous switching noise. Unfortunately, the situation is complicated and it is difficult to state any general rule on the number of balls required. As always, the performance of the desired configuration should be checked by simulation.

Layer usage can follow the bump locations, as it did in the SERDES. In our example design, ground bumps connect directly to a ground plane on the surface layer of the substrate, signals are carried on the next two layers, and power is on the lower layer of the substrate. The signals are thus in a "dual stripline" configuration, with the ground plane above and the power plane below. This is not as good electrically as the stripline of the SERDES signals, but the speeds here are lower and the requirements are less stringent. Because the signal layers are adjacent, care must be taken to control coupling between the layers. This can be done by assigning signals to balls in a way that minimizes traces running parallel on the two layers.Figure 10 shows a portion of the signal routing for the DDR.signals.

Figure 10: Example of DDR routing

Conclusion

A great deal of cooperative work was required to package this complex, high-speed IC in the desired BGA. Good cooperation and communication between IC design, substrate design, RDL design, assembly process, substrate manufacturing, and electrical modeling and simulation made this part successful.

About the author
Rich Evans, Senior Staff Engineer at STMicroelectronics, earned his BS in Physics and MS in Measurement and Control from Carnegie-Mellon University, Pittsburgh Pennsylvania, USA. He worked at Digital Equipment Corporation from 1979 to 1994, where he was responsible for many aspects of signal integrity and electrical analysis, ranging from IC packages to printedcircuit boards to networks.

Rich is currently in the Corporate Package Development group at STMicroelectronics in Carrollton, Texas, where he supplies package electrical models, guides package design to assure good performance, and designs custom Ball Grid Array packages. His current work focuses on power distribution, switching noise, and high-speed serial links.

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[芯片] Basics of chip/package codesign in a large flipchip application

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