菜鸟求组:仿真multi-threshold cmos,实现NAND gate

ak11112222ak

source 总是出现以下问题，描述的时候已经说了是接地的了啊，为什么还是会当作断开的呢？
Circuit: *Main mtcoms file

3 d- p5 n+ J# a' c2 U/ LWarning: There are nodes with less than 2 connections.
The table of nodes with less than 2 connections is generated after sourcing...



***warning***: the following singular supplies were terminated to 1 meg resistor
$ M, F5 [8 K- C" h+ B
# I4 V' z/ A: i4 @# isupply       node1            node2
vdd           vdd                  0
8 |+ Z  w3 O3 \  Z0 x+ v  dv1           a                  0
' u# G% {5 c7 g' o( x/ O: Ev2           b                  0
9 B8 U4 G8 [! }! ov3           sl                  0
4 F0 J8 ~9 s) o8 t; I

The following nodes have less than 2 connections:
-------------------------------------------------------------------------------------
| sl                 | b                  | a                  | vdd                |
-------------------------------------------------------------------------------------
, Q4 e6 q% k$ ^  H一个描述netlist的文件：
" I$ i0 j; N, \' b7 y2 ~! B

* SPICE export by:  S-Edit 15.13
* Export time:      Tue Jun 12 11:15:52 2012
* Design:           mtcoms
5 c# e' E! x) [- _* Cell:             Cell0
. [* N! @- L8 b1 e* Interface:        VResistor
* View:             VResistor
* View type:        connectivity
$ r6 a( c. c8 [* Export as:        top-level cell
6 p9 n. I& W1 g! `/ j4 g6 |* Export mode:      hierarchical
3 N" Q9 R) {3 _( u! J/ D( l* N; d* Exclude empty cells: no
* Exclude .model:   yes
* m1 |0 \3 ^2 K3 u1 y7 d/ d6 d* Exclude .end:     no
* Exclude simulator commands:     no
% B5 i8 U  l, T! d9 S* Expand paths:     yes
* Wrap lines:       80 characters
* Root path:        \\en-file\users\houx\Profile\Desktop\ankun_dong hw2\mtcoms
* Exclude global pins:   no
7 }! O& D" X% {, {6 L4 x( t( h) ?0 ~* Exclude instance locations: no
* Control property name: SPICE

********* Simulation Settings - General Section *********

7 }/ _' w" s$ o) T*************** Subcircuits *****************
. B+ w# Z5 G/ F$ p.subckt INV A Out Gnd Vdd  
+ ]- o0 g( J* E8 K
. l* S. H5 T' h* a+ Y5 ~*-------- Devices With SPICE.ORDER < 0.0  --------
) {& L) S0 i/ S+ N1 M* Design: LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
- E3 c  Z% N% e; E6 `* Organization: Tanner EDA - Tanner Research, Inc.
6 B/ m! o* I$ H8 ~$ O' t* Info: Inverter
* Date: 06/13/07 16:17:11
* Revision: 3 $ $x=7600 $y=600 $w=3600 $h=1200

1 X* C, H) j) r, M4 S, k  i$ Y$ z*-------- Devices With SPICE.ORDER > 0.0  --------
  s' x) G& c& G( D5 S  n) t4 qMN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=4600 $y=2600
+$w=400 $h=600
( D+ }+ n) m5 H  U/ `4 [MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u $
/ K' n" B4 x9 e+$x=4600 $y=3600 $w=400 $h=600
.ends


8 Q' g) J$ b6 o8 d' ~
*-------- Devices With SPICE.ORDER == 0.0  --------
***** Top Level *****
XINV_1 SL N_2 Gnd Vdd INV $ $x=350 $y=-2300 $w=900 $h=600
7 ^( z6 f2 v% _; s2 m9 b# p! b* r" u
% b( ^6 y, c- B% {* S*-------- Devices With SPICE.ORDER > 0.0  --------
8 f/ v; k& L7 u4 O1 r$ o+ C/ v1 KCCapacitor_1 VDDV Gnd  1p $ $x=3100 $y=-400 $w=400 $h=600
CCapacitor_2 GNDV Gnd  1p $ $x=3100 $y=-2500 $w=400 $h=600
: `1 [  ?5 s! {# k5 s) u* zMNMOS_1 Out A N_1 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
. U2 ^5 ~3 E4 D) J/ P9 y* \+$y=-800 $w=400 $h=600
: R! R1 r5 q! v( SMNMOS_2 N_1 B GNDV GNDV NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
3 v( D" C* V" B( K, L# B5 I# ~5 y+$y=-1500 $w=400 $h=600
MNMOS_3 GNDV N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $
+$x=1100 $y=-2300 $w=400 $h=600
, M9 j4 f; h. g; V, g. MMPMOS_1 Out A VDDV VDDV PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=300
* J8 z& O/ _* i7 g$ W+$y=-200 $w=400 $h=600
9 r4 O- @# ]' |* ], ^# a" XMPMOS_2 Out B VDDV VDDV PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1900
- ?( v' Q$ c, f+$y=-200 $w=400 $h=600
MPMOS_3 VDDV SL Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
+$y=700 $w=400 $h=600
- F9 h0 Y& p% t: R; ~
********* Simulation Settings - Analysis Section *********
0 R5 I4 ~+ `- G; Y1 P4 Z. Z.op

5 e" W% k1 Q: E$ Z) p; ?: D********* Simulation Settings - Additional SPICE Commands *********
% }+ U  ^" X; W8 @- a# s; Z4 X
.end

icy88

source接地的描述应该是 vdd vdd 0 0,你后面少个电压的值