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* Simulation of block sbTDrOut07_hmodel_01, TT Case, 85C ! F+ k5 R- V/ K) N- K% l( n, V4 ]
.options list node post probe accurate
7 s2 {: z' M, n, Q. W/ \) n/ W.options BYPASS=0) G% S3 w# B/ k' M+ b
.global SUBSTRATE VSS
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* J: M" ?. e' D' L& C7 k% a6 L********************************************************************- `9 E7 }$ U/ S. W+ r5 t. D7 E2 K
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.lib "./vendorhspice.1_0v-3_3v-G" TT' |$ |* r/ O/ I: G( z% w0 C( E
.lib "./vendorhspice.1_0v-3_3v-G" TT_hvt
8 t- X4 M! g9 Q .lib "./vendorhspice.1_0v-3_3v-G" TT_lvt+ c% H* {1 v9 z+ I) L
.lib "./vendorhspice.1_0v-3_3v-G" TT_na
* j7 H, v8 ~2 ^- e .lib "./vendorhspice.1_0v-3_3v-G" TT_BIP
2 x1 F; P3 x) D8 o1 p3 X6 @5 v .lib "./vendorhspice.1_0v-3_3v-G" TT_DIO
8 E" x. S1 m4 [, {9 X .lib "./vendorhspice.1_0v-3_3v-G" TT_DIO_hvt" h `5 P9 \. Z1 s
.lib "./vendorhspice.1_0v-3_3v-G" TT_DIO_na. Z! K2 U" ^! y* a, i4 c# Y
.lib "./vendorhspice.1_0v-3_3v-G" TT_RES3 \. X2 p$ E' b6 J, h
.lib "./ResModel.1_0v-3_3v-G" res_t
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.temp 85
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" j2 g% F9 f7 \ P********************************************************************
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.inc './TT/sbtdrout07_hmodel_01.inc'
! f8 U1 g# ]% w' h1 S9 O3 d .inc './TT/alias.inc'
% e ^5 w, a& q: U4 ~# W* .inc './data_pattern.inc'
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4 q; G. Y, `$ R& J********************************************************************4 X/ w9 d* a5 @
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********************************************************************- K; ?/ b" g% J7 S# E; C
*StatEye example circuit5 m9 q; l1 s* ^0 Q6 f
.param _BW=0.16n. g9 s( r, ` {9 L
.param trf='_BW*0.01'. @2 s' N3 \8 b
.param opfreq='1.0/_BW') D3 W2 l0 l# f" h. w2 J' c
*define ports and stimulus9 U2 G: d8 n' Z9 v8 X: m# {' V$ T
P1 data 0 port=1 LFSR (1 0 0 'trf' 'trf' 'opfreq' 1 [7,4,1])! C/ {: \7 e$ j. |: _- ~
P2 pad1 pad0 0 port=2
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VAVDD AVDD 0 dc=pwr.vdd
& R/ q7 P8 f" T- CVAGND AGND 0 dc=pwr.gnd
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* j1 P7 V0 X0 l.param pwr.vdd = 0.98
: T6 O: M+ E% X4 b.param pwr.gnd = 0.00
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Rsub SUBSTRATE 0 100' s8 E5 g/ ~" E: z1 w$ T; ^ c+ j
Rvss VSS AGND 100u# v9 l* K2 D/ p2 t
Ragnd AGND 0 100u
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3 J) h% _3 V3 C0 u" l/ r* Set up loads. ] G3 @6 \4 R# L3 F" w4 x; B
0 u o+ `; a7 [1 J. c" GRL1 pad1 vcm 50.0+ ]# D1 V1 P1 z/ U6 E+ N
RL0 pad0 vcm 50.0
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) c) X& C7 S& R* Add subcircuit with parameter values
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XDUT AGND AVDD pad1 pad0 data 'sbTDrOut07_hmodel_01'
1 ]) ?" `+ y" L$ `3 Z2 {+ sr1=0 eq3=0 eq2=0 eq1=0 Clock=Clock Wait=Wait" r& L6 v5 T/ s
1 k R( P; ?3 r7 X0 O* Set Clock parameter% H/ @8 X' J" K; e
.param Clock=6.250G
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3 \& _+ E2 A: Z& g, T* Set Wait parameter
' q& \( `! T9 M" Z2 L7 y Y.param Wait=0n
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# }7 b4 V$ |: [5 H: l P' t*.TRAN 100p 50n
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* NOTE the 100ps timestep will cause interpolation inaccuracy, but does3 V. I/ i' ~1 B. l7 J
* give a short simulation time. Serious work should be done at <10ps.
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) j1 w/ b* U- L* ]2 M1 {4 q- d# U' |*.probe" m/ R6 w) G# e- C2 ?
*+ v(agnd)
2 I5 k9 V( {' C, y& A; n*+ v(avdd)5 P1 f2 q5 V+ S0 b0 w# {" D+ C
*+ v(data)4 [3 Z- }( n9 m& _6 L
*+ v(pad0)
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*+ v(vcm)3 w _9 y9 t. B- W& f8 E/ ^
*+ i(vavdd)
0 j/ p# [: o3 G$ f8 B*+ i(vagnd)
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0 v8 q" C9 t0 ~% {/ {7 v0 a*print and probe
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.probe stateye eye(2) ber(2) eyeBW(2)
9 V/ b6 e" `; U7 ?.print stateye eye(2) ber(2) eyeBW(2)
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! \' A( ]. j0 ?4 a/ E% G*bathtub curve
+ f4 h. ?" u( I7 ]0 V, J4 t* }.probe stateye bathtubT(2,1e-11) bathtubV(2,0.0); N8 w* j0 W, K0 Z* _
.print stateye bathtubT(2,1e-11) bathtubV(2,0.0)
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.probe stateye eyeV(2,0.0) eyeT(2,1.0e-11)' R, [4 l# ] Z# c u/ s& ]
.print stateye eyeV(2,0.0) eyeT(2,1.0e-11)
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1 k0 @8 m( V4 E*measurements
" a# h) _- H5 U; W3 x.measure stateye veye1 Veye 2 time=1e-11 tol=1e-10- {4 o. W/ d& a! T7 W
.measure stateye heye1 Heye 2 volt=0.0 tol=1e-106 s3 Z! k; w4 M, n+ H, {
.measure stateye worst1 WorstBits 2 time=10p
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***********************************************************************
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; H, y% T. q( h- J.end
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$ [, A+ b& [0 M) q错误信息如下: Init: read install configuration file: d:\synopsys\Hspice_C-2009.03-SP1\meta.cfg8 P* ]" c6 k, F {; R# r( k3 l
**error** (e:\sim\stateye\sbtdrout07_hmodel_01_transmit_hspice_model\tt.sp:76)
+ ]" w- T' j2 ]* K+ U syntax error when fetching "'sbTDrOut07_hmodel_01'"
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$ i" x! i8 l6 N我用hspice2008仿真没有问题。 |
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