Cadene SPB 17.2 Hotfix下载

gleefly

转 Hotfix_SPB17.20.015_wint_1of1

游客，如果您要查看本帖隐藏内容请回复

8 r* r. C+ c' `# y
& q: {4 ^) g: O" l, }! xFixed CCRs: SPB 17.2 HF015
* t: N4 f& h: k# `4 V; Z. u03-16-2017
========================================================================================================================================================
. n1 ]+ S. y2 b5 ]/ g) Z; [$ g8 aCCRID   Product            ProductLevel2 Title
/ Y% ]; _1 S: o  B- R========================================================================================================================================================
* ~, c) M  G, ?1653366 ALLEGRO_EDITOR     INTERFACES    Unable to attach step model to symbol
2 o0 k" B- y7 \6 |7 D  _1671760 ALLEGRO_EDITOR     INTERFACES    Step package mapping window unable to display step model
$ U) y- U; o& R5 B. ~& t% M7 r+ Q1706879 ALLEGRO_EDITOR     MANUFACT      Trace gets moved to dielectric layer after using the Gloss function
1708685 ALLEGRO_EDITOR     MANUFACT      Incomplete ncdrill holes data in drl file
1712057 ALLEGRO_EDITOR     PAD_EDITOR    Changing text size and restarting Padstack Editor results in incorrectly scaled forms
1709335 ALLEGRO_EDITOR     SCHEM_FTB     Cannot import netlist from attached design
1687329 ALLEGRO_EDITOR     SHAPE         Shape is not voiding uniformly when component is rotated in 30 degrees
. {8 Z9 l% O9 B1698539 ALLEGRO_EDITOR     SHAPE         A thin shape is left when dv_fixfullcontact is enabled.
5 j; R. R0 d9 x( u1620210 ALLEGRO_EDITOR     UI_GENERAL    Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
1687819 ALLEGRO_EDITOR     UI_GENERAL    Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
8 t7 b4 p( H: X& ?$ E' I1699326 ALLEGRO_EDITOR     UI_GENERAL    Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
1711341 ALLEGRO_EDITOR     UI_GENERAL    Incorrect pad size in Padstack Editor when the German regional settings are used
1712496 ALLEGRO_EDITOR     UI_GENERAL    Padstack Editor shows incorrect values when using comma and 3 decimal places
1714744 ALLEGRO_EDITOR     UI_GENERAL    Using comma instead of dot as integer separator results in incorrect diameter value
1715714 ALLEGRO_EDITOR     UI_GENERAL    If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
1713292 APD                WIREBOND      Allegro Package Designer crashes when adding wire to a die pad
1710973 ASDA               PACKAGER      Unable to export Allegro SDA project to PCB Layout
/ M" `( t$ k) z! k5 I+ m6 M" G' l+ H1698697 CONCEPT_HDL        COPY_PROJECT  Copy project corrupts the .dcf file
9 k% j: E8 f! j0 r' S1 W* I. L1705401 CONCEPT_HDL        CORE          Alignment issues while pasting signal names in 16.6 Hotfix 084
0 W* v  Z6 o( ]' q! M1707116 CONCEPT_HDL        CORE          SIG_NAME is placed on non-grid position
1710486 CONCEPT_HDL        CORE          Rename Signal places sig_name at an incorrect position for an unnamed net
8 d3 I" Z0 P2 Z- x; `  b  n& H: X1667786 CONSTRAINT_MGR     XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
, m) ]$ }3 I) p! s1709508 SIG_INTEGRITY      REPORTS       Allegro Sigrity SI crashes when running a reflection simulation
+ B% M, h4 W3 Q: d! R1710097 SIP_LAYOUT         DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
1712964 SIP_LAYOUT         SYMBOL        SiP Layout crashes when using Renumber Pins in Symbol Edit application mode
% n" e+ H$ ?# H, S
转：Hotfix_SPB17.20.014_wint_1of1.exe 链接：http://pan.baidu.com/s/1jHFB2Pg 密码：mxnk
- b& Y; W1 u3 f/ Z% F, wFixed CCRs: SPB 17.2 HF014
( v9 f0 S7 T/ }& Q6 H; z========================================================================================================================================================
CCRID   Product            ProductLevel2 Title
# ~! c6 k$ A7 }9 T; A========================================================================================================================================================
) T; ?/ c3 s9 n  C- o1691828 ADW                COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships
1700963 ALLEGRO_EDITOR     DATABASE      Running the 'slide' command results in the cline segment losing connectivity
1685502 ALLEGRO_EDITOR     INTERFACES    The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-268
) k  w9 @2 R" c* Z1644643 ALLEGRO_EDITOR     MANUFACT      The NC drill legend does not match the drill customization data
$ h1 ~( Y! Y9 p! w# Z4 g! Q3 q1700557 ALLEGRO_EDITOR     MANUFACT      DXF output does not contain drill figure data
1660252 ALLEGRO_EDITOR     NC            NC Drill file generated with errors
7 {" e- z8 k9 t% T4 a/ ?. ?1677775 ALLEGRO_EDITOR     NC            Merging of drills not retained in database.
" x2 t' J) J2 B0 n6 g" E# O1701554 ALLEGRO_EDITOR     SHAPE         Shape spacing clearance is not updated unless the shape vertex is deleted
9 W; k8 _! y, D8 O1704669 ALLEGRO_EDITOR     SHAPE         Route Keepin is not getting created at a specific location
# r& r0 k3 H% X/ V1685995 ALLEGRO_EDITOR     SKILL         All film sequence numbers are returned as 0 when using the SKILL function axlGetParam
' |$ u3 @7 M0 ?( J* J. g1621336 ALLEGRO_EDITOR     UI_GENERAL    Changing the color visibility does not refresh the screen color immediately
1668817 ALLEGRO_EDITOR     UI_GENERAL    Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6
! ~* M1 a) R: m( D% L" i1671268 ALLEGRO_EDITOR     UI_GENERAL    Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one
1690691 ALLEGRO_EDITOR     UI_GENERAL    Reports not generating if the 'allegro_html_qt' environment variable is disabled
/ X) K0 X- C- n/ K0 U1709903 ALLEGRO_EDITOR     UI_GENERAL    Toggling layer visibility does not change the display until the mouse pointer is moved
# S- v9 a  W$ W! ?# h1647596 APD                EXPORT_DATA   Allegro Package Designer crashes when trying to export board-level components
* S; t5 E( m) p8 h) E- ~; X3 Q: T/ p: }1688035 APD                OTHER         Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers
, F/ {) Z* D- t1 |0 }) G1690777 CONCEPT_HDL        CHECKPLUS     Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase
1695987 CONCEPT_HDL        CORE          $PN placement in DE-HDL during part development is not following mouse placement
1700873 CONCEPT_HDL        CORE          With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message
7 |' _( z3 j* b* v2 K- I1702703 CONCEPT_HDL        CORE          Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011
2 t8 f: X7 h" d4 i7 b5 T  W$ ~1705999 CONCEPT_HDL        CORE          Signal naming is not working correctly in SPB 17.2
: |7 b5 @; c* {4 V9 x1677489 CONCEPT_HDL        CREFER        CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
6 ^' q! W4 ^& l3 k1698259 CONSTRAINT_MGR     CONCEPT_HDL   Unstable $LOCATION property in release 17.2-2016
# }8 w  m; t( f9 e4 [+ M0 i1702537 CONSTRAINT_MGR     CONCEPT_HDL   ECSet mapping errors reported after removing the signal models on an upreved design
1703981 CONSTRAINT_MGR     TECHFILE      Importing a technology file (.tcf) results in packaging errors
1673115 ECW                INTEGRATION   Import from external data sources (Integrations) truncates input values to 128 characters
3 [7 o! `0 e7 G, B1699395 FSP                FPGA_SUPPORT  Selecting a QSF part name in the FPGA Properties window crashes FSP
  ]0 j2 ~0 c! t/ x) R1704353 INSTALLATION       DOWNLOAD_MGR  Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'
$ [$ c% y- A+ _5 e9 j" H; z4 s1705265 INSTALLATION       DOWNLOAD_MGR  Problem installing OrCAD Library Builder from Download Manager
1 g4 h) S, D8 y1646635 PDN_ANALYSIS       PCB_PI        PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script
; X3 ]5 u8 J' m. S3 T9 w! J4 e  p
Cadence OrCAD and Allegro 17.20.013 Hotfix链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv
Fixed CCRs in SPB 17.2 HF013
( i4 T! L3 x7 |* c  {) [/ c========================================================================================================================================================
CCRID   Product            ProductLevel2 Title
========================================================================================================================================================
1567741 ADW                COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm
9 s1 I9 m5 I0 D) P5 b1697109 ALLEGRO_EDITOR     ARTWORK       Artwork not showing padstacks for the soldermask layer
, _& P7 B# _  H7 c# [+ Q1682297 ALLEGRO_EDITOR     DATABASE      Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
, A) f2 c2 U/ E$ G% [! Q8 x5 o7 j1697309 ALLEGRO_EDITOR     DATABASE      PCB Editor 17.2 uprev changes NC pins from non-plated to plated
& A7 B* y2 T  Q; d' j( M1698624 ALLEGRO_EDITOR     DATABASE      Opening 16.6 board in 17.2 converts non-plated holes to plated
, V% M' {: p& E; r! o( ?1697092 ALLEGRO_EDITOR     OTHER         axlDBViaStack crashes PCB Editor session and corrupts the board
; r7 ^/ |' P0 J5 J# b& B1687819 ALLEGRO_EDITOR     UI_GENERAL    Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
1696637 ALLEGRO_EDITOR     UI_GENERAL    Padstack Editor uses Region and Language settings for the decimal symbol
1699326 ALLEGRO_EDITOR     UI_GENERAL    Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
1616138 ALTM_TRANSLATOR    PCB_EDITOR    Board file imported from third-party tool to PCB Editor has the shapes but not the components
1666020 ALTM_TRANSLATOR    PCB_EDITOR    Board converted from a third-party tool to PCB Editor has missing components
: @  \. k" t5 f1690448 CAPTURE            CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets
5 [, O2 C' r4 \1690455 CAPTURE            CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets
1684180 CONCEPT_HDL        CORE          Message should indicate that the user needs to reload the design after setting SET STICKY_OFF
& p0 \! i$ |* g: e# M- q3 m0 k1695987 CONCEPT_HDL        CORE          $PN placement in DE-HDL during part development is not following mouse placement
1688287 CONSTRAINT_MGR     DATABASE      PCB Editor crashing while adding a net to a net group.
1675013 ORBITIO            ALLEGRO_SIP_I Failed to import brd file
1698968 SIP_LAYOUT         3D_VIEWER     3D viewer shows keepin and not design outline.
1699884 SIP_LAYOUT         ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker
; u' r& D7 k9 M* L1689969 SIP_LAYOUT         DIE_EDITOR    SiP Layout crashes when moving dies using relative coordinates
( J  X% W. |7 I, d. \& U1696239 SIP_LAYOUT         DIE_EDITOR    When using the Die-stack Editor to move and stretch wires, SiP Layout crashes
* i' X; T: y8 }- r$ ^2 d# q' Z1695372 SIP_LAYOUT         REPORTS       Running the Metal Usage reports fails on the Primary side.


4 n5 L$ g' q/ G
- k; D/ C" C) K+ k' W$ p

gleefly

Cadence OrCAD and Allegro 17.20.009 Hotfix 链接：http://pan.baidu.com/s/1pL1zPJt 密码：zs5d

sunny388

密码看不到
4 s* Y1 G* q3 e

sunny388

谢谢楼主！！

JohnyQQ

感謝大大的提供, 方便下載安裝...