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标题: SPB_16.6 27号补丁下载链接--Hotfix_SPB16.60.027_wint_1of1.exe [打印本页]
作者: Csec    时间: 2014-4-26 15:15
标题: SPB_16.6 27号补丁下载链接--Hotfix_SPB16.60.027_wint_1of1.exe
本帖最后由 Csec 于 2014-4-28 11:04 编辑 # V" q0 |. N1 s3 f' P5 y* B1 o

5 V3 B5 h9 J9 I: m6 h/ x# T. O9 Phttp://sw.cadence.com/P/download ... e4d05&file=.exe
7 Y+ q* \# ?; S/ U+ m; z更新百度网盘下载链接！/ \+ I4 H8 L" \+ K9 `6 R* U" V
http://pan.baidu.com/s/1mgwSsPy4 S" a& D. f9 d  f7 W
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DATE: 04-25-2014   HOTFIX VERSION: 027
+ v/ J+ y) y3 a& R7 [===================================================================================================================================6 b/ R. w1 x# A9 W2 h
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE) g1 M) U+ @' G; V9 E# E
===================================================================================================================================5 t$ G. t. u, h% F
308701  CONSTRAINT_MGR OTHER            Needs to delete user defined schedule in CM: ~% @3 N% C- M* q; j3 G( k
481674  ALLEGRO_EDITOR PADS_IN          No board file saved from PADS_in
4 Y" E3 Y4 V+ O" t982929  ALLEGRO_EDITOR EDIT_ETCH        can't route on NC pin and other that are not pin.
: |  h4 R( m; {% o1012783 FSP            OTHER            Need Undo Command in FSP1 Q0 r* |& Q$ C6 l4 k9 v6 |
1017381 ALLEGRO_EDITOR DRC_CONSTR       Need Dynamic Phase to be able to measure back to the Drive Pins.- t; m0 C2 n; l" M% L. Y2 Y. O
1072673 PCB_LIBRARIAN  GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
& K# ?7 ?7 \. E2 ^/ ]. [" l1073231 CONCEPT_HDL    CORE             Copy-paste of signal names goes off-grid in Windows mode./ e  \$ i/ k& d3 R. J
1105371 CONCEPT_HDL    INTERFACE_DESIGN Strange behavior when shorting two Net groups! H& ~! D& N, R! q% f( u
1116498 CIS            LINK_DATABASE_PA link database with modified part results in Capture crash5 x  W0 N* e( i4 `+ Z
1118632 ALLEGRO_EDITOR GRAPHICS         Text display refresh issue while in Edit > text command
, V- X, ~. g4 C+ }$ L1155821 SIG_INTEGRITY  LIBRARY          Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
3 A1 X0 D0 Y/ X5 P, e2 v0 H1157372 ALLEGRO_EDITOR DRC_CONSTR       Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
( g( {( M( Q' D# w1171951 ALLEGRO_EDITOR CREATE_SYM       Jumper has a limited of count when it add to list.* ], a  p/ ?- Q! B6 b
1180871 CAPTURE        LIBRARY_EDITOR   Copied parts don't retain pin name and pin number settings) d2 G% j8 v6 w, S8 q4 b" \
1185575 SIP_LAYOUT     DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
1 f$ H! C6 N5 y) `$ ^5 ]1185772 PCB_LIBRARIAN  CORE             VALID_PACK_TYPE warning when cell was opened in PDV
6 ?& i! w! n2 u- F4 ~+ n2 c1192377 CAPTURE        SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
0 @: ?0 e' z# p5 N4 K1202654 ALLEGRO_EDITOR GRAPHICS         Zoom using mouse wheel shall maintain the center co-ordinates2 o# G8 M3 Q# T5 n. Y3 E* s0 {
1208031 ALLEGRO_EDITOR INTERACTIV       Snap to Pin for via during Copy command do not snap to connect point everytime
" ~. k- T% s7 S0 z) x1208478 PSPICE         PROBE            Attached project gives overflow error with marching ON.# B# K+ L! p8 ?0 U- _
1210015 CONCEPT_HDL    CORE             The value of $PN should be not turned on spin or rotate symbol
3 I( k% Q! z; g7 }" `' E4 d- [1210425 CONCEPT_HDL    CORE             When moving a circuit tool reports that connectivity has changed
7 W) ~) S1 |8 z* {% H+ Z" d) m1215858 ALLEGRO_EDITOR SHAPE            Force update does not void cline with the shape
9 ]$ p/ B7 g" u4 L  ~: G0 Q1215906 ALLEGRO_EDITOR SHAPE            Dynamic shape fill smooth failed when copying to other layers
( m& c( S1 u5 U5 |3 o! y  l) O1216358 CONCEPT_HDL    CORE             Can we improve our export BOM function to check if user did export physical function before exporting BOM?1 p  a5 O6 C/ T3 C3 z
1217364 CONCEPT_HDL    OTHER            Netlist reports fail because error: GScald failed.* F# F8 O. ]6 C* T! S& d# g6 }
1217529 CONCEPT_HDL    CORE             ADW checks do not catch single quotes in PTF values
+ `7 C  x/ V" ?. g( }# u1217556 F2B            PACKAGERXL       signal name change not sent to Allegro after packaging+ Q' _0 l5 }! o  e! d) D
1219283 ALLEGRO_EDITOR DRC_CONSTR       Show constraint is inconsistent when displaying region information8 r  F3 q' d3 t$ h- I
1220078 F2B            PACKAGERXL       Export Physical crashes when ALL the part pins are added6 L/ |9 J- d. r$ b- O
1220393 CONSTRAINT_MGR CONCEPT_HDL      HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
4 Q7 T6 j6 J  W1220540 ALLEGRO_EDITOR GRAPHICS         Need an option to see the pads inside the internal plane shapes6 M% w3 ^0 E# k( _
1220936 CONCEPT_HDL    CORE             About crash by vpadd/vpdelete command on Linux
. D/ H+ K2 C$ d8 a5 E1 I( ~% A) R1221059 ALLEGRO_EDITOR DRC_CONSTR       Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
4 w" g9 u$ M" k/ Y1221182 ADW            TDA              Team Design with SAMBA
8 w- J6 s2 n6 W1222442 CONSTRAINT_MGR UI_FORMS         Duplicate pin pairs appear in DiffPair* g) M, H3 d. f  ^& @' v
1223175 CONCEPT_HDL    CONSTRAINT_MGR   Schematic crashes when opened! [8 M0 [2 z4 w+ X
1223533 ALLEGRO_EDITOR GRAPHICS         Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?4 c" W* l. P- R. q1 d# N1 e: m
1223680 CONSTRAINT_MGR ECS_APPLY        Improve ECSet mapping by allowing user to address ambiguity of Parts& `; C, a2 l% r: Z0 K
1224156 SIG_INTEGRITY  SIGWAVE          Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
/ u! R7 ^7 ~5 J) g+ H) C1224417 ALLEGRO_EDITOR PLOTTING         Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
0 }: Q: [) W- I1 q/ F2 O: L  H1224704 F2B            DESIGNVARI       There is no lock for the variant.dat file - multiple users can open the editor) Y0 }$ G, n5 g; ^5 }# A
1224968 ALLEGRO_EDITOR INTERACTIV       Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
8 ~- m& H3 @. x+ p- x1224982 CONCEPT_HDL    PDF              commandline publishpdf does not work when there are spaces in the path. p; p! e+ V' M, H& b3 `
1225114 CAPTURE        GENERAL          H-pins added after netgroup pin get color as of netgroup pin' M& I: ?) [/ F( s* k2 b3 @
1225494 CAPTURE        DRC              Different DRC results for Entire design and selection
- i$ Y' v7 |- P/ q4 S1226153 ALLEGRO_EDITOR INTERFACES       Export STEP should include PART_NUMBER property
3 |% F' }5 u1 h7 h1226235 ALLEGRO_EDITOR EDIT_ETCH        Enhancement to include Pin_delay of descrete forming Xnet
6 Y; N$ j& \1 X) B# w1226372 CAPTURE        GENERATE_PART    ENH: Functionality to add pin spacing in New Part From Spreadsheet8 {9 C/ x" w1 x8 {
1226477 CONCEPT_HDL    CORE             DE HDL縮 `Allowed Global Shorts?  function is inconvenient for Global Signal3 b; Z# W2 S/ S' M( @" `
1226813 SIP_LAYOUT     LEFDEF_IF        ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file7 V- K: e  o# o$ J. [
1227453 ALLEGRO_EDITOR SHAPE            Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors" w) _5 F, ?( }
1227461 ALLEGRO_EDITOR SHAPE            Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,82 Y7 @. m! f5 P' W& a
1227469 CIS            DBC_CFG_WIZARD   Oracle Views not visible on Step2 of CIS Configuration
7 c. H8 B) D3 f, J2 h) u) i1227780 CAPTURE        ANNOTATE         Inconsistent behaviour when annotating heterogeneous part
% \3 Q7 V, ?6 L; ?1227831 CONCEPT_HDL    CORE             Pin text and H-block name in upper case9 h8 t3 t% h: g! H$ Z
1227954 CONCEPT_HDL    OTHER            supress check for global signals when wires are unconnected to pins
) f! A$ G/ G2 ?- M  J1228190 ALLEGRO_EDITOR OTHER            Unable to close the 'usage' window during license selection
2 l  m$ n- ^# |2 A0 m+ i  i1228899 CONSTRAINT_MGR INTERACTIV       Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
: p9 N: R6 f5 d& T4 T7 I/ z1228934 ALLEGRO_EDITOR EDIT_ETCH        The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.: f* A' a1 w4 v; z1 I/ [1 L3 W
1229316 ALLEGRO_EDITOR EDIT_ETCH        When routing with Hug only enabled we were able to route through other routes(sometimes Hug).7 O/ k3 w( \2 Y! u
1229545 CONSTRAINT_MGR OTHER            Allegro indicate bundle scheduled nets in CM
' K( [  R9 Q& X) g) B1230056 ALLEGRO_EDITOR GRAPHICS         Bug: 3D View of Mechanical Symbol with the drill hole defined
6 e( q* I/ w  y* c$ ~1230432 CONCEPT_HDL    CORE             No Description information in BOM2 A1 {. ^+ I' n' @5 e( `
1231148 F2B            DESIGNVARI       The variant.dat file is not updated with library PTF changes
3 j0 I: l9 @  }1231625 F2B            DESIGNSYNC       VDD at command line needs to support sch2sch and test variable to write out report files! Z1 V: t) H. e0 m! L( o7 A
1231697 CONCEPT_HDL    CORE             If any locked files exist force a pop-up dialog restricting certain commands
( e/ J+ I4 z2 D$ a- i% e1231767 CONCEPT_HDL    OTHER            Unable to find under the search options single bit vector nets- e, K( z$ B: d9 a+ E+ f# Y! l
1231961 ALLEGRO_EDITOR SHAPE            Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
0 @% @: r5 n6 Y1232100 CONCEPT_HDL    SKILL            Unable to execute the SKILL commands in viewer mode: ~# E% G0 ?) b( z
1232336 CONSTRAINT_MGR CONCEPT_HDL      cmFeedback takes 5hrs to complete during Import Physical
& M: k/ V7 l9 R% }+ c2 A" g1232710 F2B            DESIGNVARI       Dehdl crash while moving component in variant viewer mode
/ C! k: k) V- Q" @1233894 F2B            PACKAGERXL       The page data is missing in the pst* and PCB files
! x3 h- t- v1 a4 d: J  S1235785 CONCEPT_HDL    CREFER           cref_from_list custom text is not subsitituted in complex hierarchy
) C  S$ B3 w- H6 \0 P, X  s! A1235928 CAPTURE        SCHEMATIC_EDITOR OleObject modifications not saved1 U9 }4 B1 o0 {7 n( _$ W7 m( n
1236065 CAPTURE        PART_EDITOR      Mirrored part after being edited get pin name locations incorrect
! ?+ t4 P' f5 A# A! B1236071 ALLEGRO_EDITOR SHAPE            Airgap for Octagonal Pads ignores DRC Value when Thermal set5 @3 Q) `/ g7 ~# N3 Y
1236072 CONCEPT_HDL    CORE             Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic! J& Q/ s0 o5 U: l, M8 D
1236161 CONCEPT_HDL    CORE             Import Design shows the current project pages  \/ F* M1 j8 P% p8 P2 G+ V% [
1236432 ALLEGRO_EDITOR PADS_IN          pads_in doesnot translate via and shape in some instances.
/ E# a2 m+ X+ N1 g6 r3 ^1 T1236557 CONCEPT_HDL    PDF              Running Publish PDF on command line in linux doesn't output progress until completion- U3 M( g; C* V6 a5 S" g% ?: U
1236589 CONCEPT_HDL    PDF              Enhancement license failure error should appear in pdfpuplisher  log file
- f9 u1 m5 Z8 p1236644 ALLEGRO_EDITOR EDIT_ETCH        create fanout deletes shape$ v0 a8 g4 g: a; X. \7 x
1236689 ALLEGRO_EDITOR GRAPHICS         Graphics displays extraneous lines when panning or zooming
4 Q; z# \& R1 S1236781 F2B            PACKAGERXL       Export Physical produces empty files+ E" v. D# a( R  B( t9 y1 ~) S' A0 {
1237331 PSPICE         ENVIRONMENT      pspice.exe <cir file name> - hangs when run
1 a! t& D  `' |0 K$ f1237400 CIS            EXPLORER         Capture hangs on 2 consecutive runs of `refresh symbol from lib? command& Z7 |" D& g! H2 D
1237437 CONCEPT_HDL    CONSTRAINT_MGR   CM Crash when saving after restore from definition
2 k5 e5 M7 D! F2 S4 f* x6 ~" ^1237862 CONSTRAINT_MGR OTHER            A way to remove the RAVEL markers from the Constraint Manager.: ?# L) Y( l! D8 g  C; n2 B1 m2 B
1238852 CAPTURE        GENERAL          signal list not updated for buses
% W  Q6 w" P  J% G. z1238856 FSP            DE-HDL_SCHEMATIC FSP schematic generation crashes" y5 w% `/ s7 e2 B  n/ A, O
1239079 ALLEGRO_EDITOR INTERACTIV       The 16.6 Padstack > Replace function leaves old padstack.
: k! v7 t) x' \7 Y* F1239706 CONSTRAINT_MGR ANALYSIS         The reflection result on a differential signal in the CM when Measurement location is DIE
4 p) p" H, V! D1239763 PSPICE         PROBE            Cannot modify text label if right y axis is active
! F2 o# K3 T# S# s1 B1240276 ALLEGRO_EDITOR GRAPHICS         Printing to PDF from SigXp is giving unreadable images# z: D5 d3 E) |4 H) S- I
1240356 CAPTURE        IMPORT/EXPORT    Can縯 import SDT schematic to Capture., y  m3 A: j8 O$ O
1240502 F2B            PACKAGERXL       Corrupt cfg_package does not stop PackagerXL from completing
3 {, p; K: S9 K2 W  s1240607 ALLEGRO_EDITOR OTHER            Footprint of screw hole got shift in DXF file$ ]) j# Y/ S  p7 ^0 r: k! w9 w
1240670 ALLEGRO_EDITOR PLACEMENT        Select multiple parts and Rotate makes them immovable) s/ ]. F1 _' m, U8 t) k2 l- y
1240773 CAPTURE        DRC              DRC check reports error for duplicate NetGroup Reference in complex hierarchy
' w* p% y8 A9 G; Y4 Q1240845 SIG_EXPLORER   EXTRACTTOP       Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
9 P" p' l) @: ?6 ]3 a% T) W1241634 ALLEGRO_EDITOR OTHER            Netshort for pad-pad connect not working3 _( |8 Y3 W# C8 R: \6 y0 `8 s( I
1241776 CONCEPT_HDL    CORE             In hierarchal design not all pages are getting printed.- `" P, p2 w  `, l  N
1241788 CONSTRAINT_MGR CONCEPT_HDL      Issues with changing focus in Constraint manager using keys on keyboard
% L+ s, l, j7 v: l- U! M1242683 ALLEGRO_EDITOR INTERACTIV       Color View Save replaces file without warning5 s, `$ l9 @! d# b
1242818 ALLEGRO_EDITOR PLACEMENT        Placement edit mirror option places component on wrong side
2 p4 R3 i1 i9 o8 O- ~8 J, I1242847 ALLEGRO_EDITOR GRAPHICS         Need an option to suppress Via Holes in 3D Viewer
1 V/ @2 I8 V9 o! M1 \- Q1242923 ADW            COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results+ y, n  @! s2 j4 {- Q
1243609 CONCEPT_HDL    CORE             autoprop for occurrence properties" ~* N0 H4 P7 _3 x
1243682 F2B            DESIGNVARI       after undocking variant icon cannot be redocked back to GUI
2 i% I$ ?  N! h' R" C1243686 ALLEGRO_EDITOR GRAPHICS         Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.# j7 C9 |# P% `) X, }( H$ G
1243715 CAPTURE        PART_EDITOR      Pin name positioning get changed after rotating or mirroring
& A0 r+ K/ j7 q% h% G7 t2 U# _. x! ~- c1244945 CONCEPT_HDL    PDF              PDF Publisher does not include image when file is not located in the root folder" P- l% s) G$ g9 c
1245568 CONCEPT_HDL    CORE             Dual unselect needed for wires attached to other net/source and property is not deselected when component is
/ s& R5 g; D. B" {+ H  N1 w1245819 F2B            PACKAGERXL       wrong injected properties information passed during packaging of the design0 }* [0 r/ c1 [5 x, {
1245916 SCM            CONCEPT_IMPORT   Where does the folder location reside for DEHDL imported blocks?4 n. y5 t/ R1 x1 M
1246347 CONSTRAINT_MGR CONCEPT_HDL      DEHDL crash if environment variable path has trailing backslash character
7 p, u9 I0 y+ \+ N1246896 ALLEGRO_EDITOR DFA              DFA_UPDATE on Linux reports err message if the path has Upper case characters
4 D0 |( L" ~3 d. C  O, A6 M& e- z1247019 SIP_LAYOUT     DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown5 r4 o" y% o- T- R  u1 s. G9 Y( m
1247037 CAPTURE        LIBRARY_EDITOR   Copy & Paste of library parts resets pin name and number
1 e  Q5 m1 W. U% H1247089 CONCEPT_HDL    CORE             Group Align or Distribute > Left/Center/Right crashes DEHDL5 V# [+ p. L4 k" h# c. q
1247163 CONCEPT_HDL    PDF              Physical Net Names in PDF not maintained* P# b: O; U1 x8 \1 c$ Q% D7 z0 R
1247462 CONCEPT_HDL    CORE             Text issue while moving with bounding box( x; x' x, s  I9 b* s
1247464 ALLEGRO_EDITOR UI_FORMS         When using the define B/B via UI the end layer dropdown arrow is partially covered9 W) X7 \* P! e/ c* f
1249063 CONCEPT_HDL    CONSTRAINT_MGR   CM and SigXP doesn縯 respect PACK_IGNORE at components- [' G) G' B1 T) ]& O: M( E
1250270 CONCEPT_HDL    CORE             Part Manager Update places wrong parts
. {- L' W9 N7 L0 K: l9 [% l. D1251206 ALLEGRO_EDITOR ARTWORK          Aperture command cannot create appropriate aperture automatically from design.
- i* ^9 n" \1 ?: L3 \1251356 ALLEGRO_EDITOR INTERFACES       Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint( Q2 S5 M% n9 Q6 _2 m# ?
1251845 ALLEGRO_EDITOR EXTRACT          Crosshatch arcs do not extract correctly
3 Z$ L4 i& B# H& W% j' ]1252143 APD            OTHER            When using the beta "shape to cline" command the tool is removing the shape instead of converting it.8 g+ X# k- O0 d9 Z' _" _6 V/ t' q" r
1252737 SIP_LAYOUT     OTHER            SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies3 P1 a1 h' y' X1 `6 I7 U6 b% [6 R
1253424 SCM            SCHGEN           Export Schematics Crashes System Architect7 X$ a  e7 G. V# J3 h' M
1253508 ALLEGRO_EDITOR INTERFACES       Bug - Export IPC2581 exports Crosshatch shapes as filled
, P: \% H1 ~+ s3 V3 B8 A' X  p; V1253554 SIP_LAYOUT     OTHER            SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing1 N3 s. A# ?# H6 @% u* G
1254578 SPIF           OTHER            Specctra crash with Error -1073741819 for Auto router2 Y( V3 ]7 J) m/ }* O% H
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK   adding nets to a net group causes constraint assignment error
8 e* o" c- O" H, O) z: i& ?2 i1254676 GRE            IFP_INTERACTIVE  Rake Lines disappear when Auto-Interactive Breakout is enabled.
+ L8 j0 B( M$ ?+ l" z7 E1255067 SIG_INTEGRITY  REPORTS          Allegro hangs on Net Parasitc Report generation$ M9 T; y9 w7 u5 {& h* I9 D/ v; Z, v
1255267 ALLEGRO_EDITOR SKILL            axlDBGetPropDictEntry does not return a list of all objects
9 V" S- V0 D( d" y1255383 SIP_LAYOUT     IC_IO_EDITING    cant move bumps or driver in app mode
3 S: Q7 |; d+ o1255703 ALLEGRO_EDITOR SKILL            axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided" }8 h. A6 F6 Y5 I) X) k* Y& r
1255759 ALLEGRO_EDITOR INTERFACES       Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
$ S1 \) {  a. A4 H4 e; t1256457 CONCEPT_HDL    CONSTRAINT_MGR   Extracting a XNet from CM crashes the tool' Q* t- h5 {( F$ m5 e
1256597 GRE            CORE             Allegro GRE crashes while running Plan Spatial, on a particular design
3 i" g2 }* n! j1256650 ASI_PI         GUI              PFE - Cannot generate model file error when using company decap library
5 u, j% o: `) i. l, A" r. @" g' z1256837 SIP_LAYOUT     DIE_EDITOR       Open and close of die editor takes too long0 s9 Y8 |7 j7 u  C: Y
1257732 CONSTRAINT_MGR OTHER            Bug - Export Analysis Results in CM makes Allegro crash
: x( b' Z! ^" s0 _; Z1257755 ALLEGRO_EDITOR OTHER            Editing time in Display > Status seems to be logging wrong time9 Y; Z  n8 s5 m5 c( R$ @
1258029 APD            WIREBOND         The bondwire lost after import the wire information6 v; R+ j6 I. f  K4 Z
1258979 APD            NC               NC Drill: There is difference of number of drills.
, `: u$ s, b9 m2 G. E1259484 SIP_LAYOUT     OTHER            SiP - calc min airgap calculate minimum airgap beta feature improvement1 u( o7 }2 G. p: r
1259677 CONCEPT_HDL    CORE             hier_write -forcereset cause component prop change.  |8 Z$ D7 j% H# W* }" p6 C- @
1259913 ALLEGRO_EDITOR UI_FORMS         Unable to save setting of "use secondary step models in 3D viewer"
! M3 ~0 X7 m% c6 w7 e/ F. R8 f4 D6 `1261758 ALLEGRO_EDITOR EDIT_ETCH        Auto Interactive Delay tune (AiDT) is deleting clines9 @1 \$ ~! k4 t+ A4 t9 h" t3 F
1262543 ALLEGRO_EDITOR MANUFACT         merge shape results in moved void: d. }+ `, [: _& V
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK   XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
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作者: pzt648485640    时间: 2014-4-26 16:08
谢谢楼主的分享
作者: finezhang    时间: 2014-4-26 17:09
好像不能下载
作者: wu5163    时间: 2014-4-26 17:16
finezhang 发表于 2014-4-26 17:09) w( m: R% {' Y+ ~" }- o$ n
好像不能下载

- r0 @/ J& h7 w  k' c% U谢谢楼主的分享            好像不能下载
作者: mengshang    时间: 2014-4-26 17:30
我用迅雷下载，速度比较慢啊
作者: zhongwaiting    时间: 2014-4-26 17:39
本帖最后由 zhongwaiting 于 2014-4-26 17:48 编辑
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6 r( W! G+ z5 T9 ?* \: k) S2 C0 Q请哪位大虾给一个百度网盘链接！( W5 e4 ~4 |9 p7 z; T- }" C: ?* I3 t
网络的下载速度跟不上软件的更新！
作者: Vegeta    时间: 2014-4-26 21:30
请问怎么打补丁？需要重新安装Candence么？
作者: rufeng888    时间: 2014-4-27 07:12
16.5补丁出到多少啦？
作者: mengshang    时间: 2014-4-27 07:31
现在Download失败了
作者: rainbowII    时间: 2014-4-27 07:39
链接无法打开，请放置在百度网盘
作者: wangerfeng    时间: 2014-4-27 21:13
链接无效，不能下载，鉴定完毕。
作者: cdw1986    时间: 2014-4-27 21:59
提示: 作者被禁止或删除 内容自动屏蔽
作者: amote    时间: 2014-4-28 08:49
谢谢楼主分享，请问有转存baidu盘的么，这个链接下载不了
作者: zeiss    时间: 2014-4-28 08:59
谢谢啊，要是有其它网盘的下载地址就更好了，cadence下载有点慢" h& z0 T- B5 U$ l3 I( L$ [
不过还是要十分感谢分享
作者: tubegong    时间: 2014-4-28 10:06
下不了
作者: Csec    时间: 2014-4-28 10:48
更新百度网盘下载链接！$ N& o: L/ C7 p: L
http://pan.baidu.com/s/1mgwSsPy
作者: Csec    时间: 2014-4-28 10:49
finezhang 发表于 2014-4-26 17:099 y  T. q% {0 ]7 C
好像不能下载
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已更新百度网盘下载链，见16楼！
作者: zhongwaiting    时间: 2014-4-28 11:04
Csec 发表于 2014-4-28 10:48
/ G- B2 K5 j8 H更新百度网盘下载链接！! A: P- P! b7 }- d! K. R( N
http://pan.baidu.com/s/1mgwSsPy

; r( N4 V5 D! l" g% h非常感谢LZ的分享！
作者: tubegong    时间: 2014-4-28 11:06
谢谢楼主，
作者: wolfshiao    时间: 2014-4-28 12:50
感謝樓主大大的無私分享囉!!
作者: amaryllis    时间: 2014-4-28 12:55
楼主好人，楼主威武
作者: amote    时间: 2014-4-28 18:25
Csec 发表于 2014-4-28 10:482 ?) D( M9 C. v# X; m. R% j
更新百度网盘下载链接！; {" ^! M4 s5 K  a
http://pan.baidu.com/s/1mgwSsPy
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谢谢！
作者: zxpchx    时间: 2014-4-28 21:08
嗯，这个快。谢了！
作者: dongreenew    时间: 2014-4-28 23:35
感谢分享
作者: szm2000    时间: 2014-4-29 06:45
谢谢楼主啊，太及时了！
作者: inspiron1501    时间: 2014-4-29 07:31
一个多月没更新了，果然在憋大招，这bugfix真长。
作者: rainbowII    时间: 2014-4-29 11:13
amote 发表于 2014-4-28 08:49# ?/ h9 h' U1 }" O5 ~- C3 J
谢谢楼主分享，请问有转存baidu盘的么，这个链接下载不了

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作者: rongzhai    时间: 2014-4-29 16:00
这个补丁安装似乎有问题啊
作者: suiwinder    时间: 2014-4-29 23:25
so nice so good. thanks a lot in advance.
作者: 冠少H    时间: 2014-4-29 23:26
不知道哪里可以下载16.5的呢，下了个16.6的好像没安装成功
作者: myexpma    时间: 2014-4-29 23:51
安装时前面有几个图片出现crc错误，忽略过去了，但是后面有exe文件也有crc错误，因此中止了更新，希望版主能重新更新软件。
作者: elm99    时间: 2014-5-2 14:10
谢谢分享！
作者: wqnet    时间: 2014-5-2 14:58
myexpma 发表于 2014-4-29 23:51
9 ?0 g# d! N9 T, l1 K6 b安装时前面有几个图片出现crc错误，忽略过去了，但是后面有exe文件也有crc错误，因此中止了更新，希望版主 ...

$ T9 _. A$ j5 F% c应该是百度客户端的问题，一旦断线，重新开始的东西就不对了！遇到过好多次。文件本身应该没有问题，刚下载，数字签名没问题。
作者: zhjinkun    时间: 2014-6-22 13:27
链接又挂了
作者: iseariver    时间: 2015-10-13 16:30
下载不了了



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