标题: Hotfix_SPB16.60.019_wint_1of1 [打印本页] 作者: pzt648485640 时间: 2013-11-18 09:19 标题: Hotfix_SPB16.60.019_wint_1of1 本帖最后由 pzt648485640 于 2013-11-19 08:22 编辑 + p! ?. @* N7 u
) Q7 @$ k& ]! x" g- J0 Z* `! P http://pan.baidu.com/share/link? ... 9&uk=2033524562 " ]% Z* h1 S9 J9 D L. n' D$ d. {* e- g4 z5 r; N+ r: U 9 C$ `5 U# y# ^9 L% p& I# {DATE: 11-15-2013 HOTFIX VERSION: 019% g; ~: z7 s& U4 v. K1 @( F
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=================================================================================================================================== , y, {3 B, P( }5 } 8 y4 K& r3 ~/ l" |' G9 b. F$ W `, VCCRID PRODUCT PRODUCTLEVEL2 TITLE # R1 M7 y7 c* V# U" y- m- h- [! c! ^
=================================================================================================================================== 6 w. @7 i6 e0 M0 M' d! C - p# E) T( B6 j1 {1176155 CONCEPT_HDL CORE Graphics remnants with 16.6 QIR 32 ]; Y: V$ B4 M A4 M
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1178272 CONCEPT_HDL OTHER Verilog netlist does not include split blocks correctly' i$ F0 w$ F t9 G! p4 q/ v+ V1 d. U
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1190782 FSP FPGA_SUPPORT Support for Altera > 5SGXEA9N2F45 device.- v; V- R T5 l1 S4 C6 L
4 m' j d: i& F) e# k3 u3 z1194140 ADW LRM SYNC_PROPERTIES is not resolving issues a based sync_properties settings : i* j( Q. Y D, b7 T; c: Z* e- j8 b# M' ?& ~
1195744 APD EDIT_ETCH Diff_Pair routing fails on certain Uvias in the pair.* w! ^* J- P0 C7 Y- z2 s4 C
}( I" X2 N0 z' v: @1 y( E1196704 ALLEGRO_EDITOR INTERFACES ENH: During ipc2581 export checkboxes corresponding to ¿Miscellaneous Image Layers¿ should automatically get selected 0 b8 {- C u. k1 h+ S5 W8 S A) t 2 A& t! B8 t$ X7 j# k+ k4 f# X# c1198340 ALLEGRO_EDITOR OTHER Multiple -product option on the Allegro command line does not access the second -product9 ~/ @$ K' B5 `
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1198596 ALLEGRO_EDITOR INTERFACES When copper thickness is increased for the outer layers, step Viewer does not show correct component position. 0 ^9 U2 P4 h4 {* `+ v ?, {3 b* r# J! M$ T1199673 PCB_LIBRARIAN OTHER Component Browser fails to load footrpints if they are set with UNC path 3 y3 ?. D- l+ J & B4 Q; `- G! Y8 a1 g8 v* y1199889 ALLEGRO_EDITOR DATABASE Allegro crashing with latest hotfix. - I+ o4 s8 n/ H z( m. S 6 A2 L* h! l# E1200303 ALLEGRO_EDITOR GRAPHICS 3D Viewer does not update after changing STEP model mapping) D9 C: h H G# [; O; d
. l S- Q2 M6 n7 K9 M1200449 ALLEGRO_EDITOR REPORTS Allegro crashes when generating Net Loop Report. ' v: [( R% ^- ]& l3 H& T/ F$ U* T' x
1200915 ALLEGRO_EDITOR DATABASE Reducing accuracy of this specific design crashes Allegro% n/ Y$ X5 I1 s n( w
% `( Q( K' s, u. F# ^' E1201011 ADW COMPONENT_BROWSE Component Browser crashes in DB mode ^; x- D; @" }
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1201376 ALLEGRO_EDITOR INTERFACES Allegro hangs when trying to map a specific STEP model to a package drawing. 9 a8 S9 h1 W3 r . n: \& k& T+ l/ C. W, h8 S- P1201897 SIP_LAYOUT IMPORT_DATA BGA Pin Colors not matching the Colors defined in the Symbol Spreadsheet after updating. $ }; I% _% U. Z' O5 |0 L! m2 y+ u+ d2 G. |9 y
1202709 ALLEGRO_EDITOR INTERFACES STEP File generated from Allegro is not overwritten when the variable "set ads_textrevs * z) r% {+ K5 _; f/ R9 p% n : F+ B( a( E7 @3 B# t1202820 ALLEGRO_EDITOR INTERFACES Different xml generation for same step model on S106 and S017 ) F& V) D; A* X0 p . Q. r+ l# s; l& f1202842 ALLEGRO_EDITOR INTERFACES Step model invisible for one pin dra in allegro 16.6 symbol editor q. A* M8 W) N1 x2 E
. m' H" v2 i+ w1 r4 Z0 J- Y( o1202983 ALLEGRO_EDITOR SHAPE Shape voiding creates DRC with Route Keepout $ U" T$ R' H% O0 I/ ` & E# R* ~$ [4 P) q1203125 ALLEGRO_EDITOR OTHER Exporting STEP file with External copper enabled does not show all copper when viewed with Solid Edge or Inventor+ q; \. y1 @% I& s6 ^$ E+ w
; _* o# w- W# I# s! d& Z( a5 F1203236 ALLEGRO_EDITOR INTERFACES IPC2581 output with crosshatched shape is not correct1 }: f1 J: I* H: |8 Y
3 Z ^' E, G1 l& F+ n* y. Z- a1203995 CONCEPT_HDL CHECKPLUS CheckPlus rule, local_signal_no_offpage_body, getting an incorrect failure.: V8 Z1 E( }+ l, d* K
/ N$ S- O7 o8 G4 b1204629 ALLEGRO_EDITOR SKILL axlUIDataBrowse crashes the editor or returns error ! a4 \9 X! h/ T. Z8 s. H8 H9 t1 z ) L6 ~ g4 G2 V- z% o! }# h1204640 SIP_LAYOUT DIE_EDITOR Concurrent co-design update fails( c# T" h- w, L* v
0 [# o+ y% e! i& F: _- W3 B/ U1204881 SIP_LAYOUT BGA_GENERATOR Pin numbers are messed up after deleting a pin at a staggered bga . \) V. i: z8 c# s5 |7 l3 U; V; I/ r1 A% S- A' e. }7 ^# O X x. U
1204885 CONCEPT_HDL CONSTRAINT_MGR Cant assign discrete models after the wrong model was removed. % B8 q% n: T3 l5 |1 b8 Y8 s1 i9 L 4 X4 ^3 E5 {5 M0 n/ S4 M1205374 ALLEGRO_EDITOR OTHER pdf out command creates incorrect drill Symbol Characters placement in pdf file when setting film mirrored. % u; r, z9 w; Y3 s; r% `- l: t8 H8 g7 c' L
1205729 SIP_LAYOUT DIE_EDITOR update of codesign db fails on exit from die editor . q+ ]) r- G1 y2 z @. B: G0 ]
1205801 ALLEGRO_EDITOR OTHER Tool crash when do export IPF. & C) `, j4 Y( v) k1 j& w0 U 1 B+ R8 C5 l& l6 A- w/ X1205881 CONSTRAINT_MGR OTHER In CMGR , Objects > Create crashes Allegro 2 W2 R" J( N: ]$ D _ 6 p5 k! l @3 d# I; ^ # W T) M0 ]" F& {) J+ d作者: amaryllis 时间: 2013-11-18 10:55
这个得顶起吧作者: wolfshiao 时间: 2013-11-18 12:51
趕快來下載囉!!! ^0 K7 Y; T8 Z; I. B謝謝大大無私的分享!!!作者: cxt668 时间: 2013-11-18 22:32
先收下了。谢谢!作者: zhongyiwaiting 时间: 2013-11-19 13:09
谢谢LZ的分享!!!作者: 鱿鱼1 时间: 2013-11-19 14:46
能给详细点吗?我有点不太明白作者: lans0625 时间: 2013-11-19 20:10 作者: owenn 时间: 2013-11-20 05:43
谢谢分享作者: wanruyi 时间: 2013-11-20 08:56
破解没有问题吗? % |5 T8 r' q$ z& B" j3 [; v. T( B+ D$ `. f3 g- X
有没有测试呀?作者: allanwang 时间: 2013-11-20 09:07
谢谢分享!!!作者: jinlong_hust 时间: 2013-11-20 09:54
软件更新的速度真快作者: wangshilei 时间: 2013-11-20 10:02
谢谢分享,更新的真快作者: hzqydq 时间: 2013-11-20 10:18
顶!!!!!!!!!支持!!!!!!!作者: mengshang 时间: 2013-11-20 12:02
感谢分享啊作者: mengshang 时间: 2013-11-20 12:38
怎么下载下来只有1M作者: mengshang 时间: 2013-11-20 12:59 http://www.orcad.nl/patches/Hotfix_SPB16.60.019_wint_1of1.exe,大家试试这个链接作者: fanscs 时间: 2013-11-21 14:29