" G% u7 D) a2 c4 ?* g* |6 E2 @# X4 `) e5 b4 \' g
DATE: 11-15-2013 HOTFIX VERSION: 0196 d6 L1 i& j5 ]1 @; D) Y% w5 }2 h
- g& f. W/ L6 t) I4 D
===================================================================================================================================( T9 {1 X# h' F' \, K. H
_4 i- E8 x- D3 u9 N* S( h3 y
CCRID PRODUCT PRODUCTLEVEL2 TITLE1 ?9 u) P, P" v
! X# p: o5 L0 V# `4 t0 e: X
=================================================================================================================================== " V# ^! B1 X7 c8 c4 u$ Y6 S6 A3 T" Z* T
1176155 CONCEPT_HDL CORE Graphics remnants with 16.6 QIR 3) F2 q& L, q# g2 X' f) {1 X& O
# |* |! H% ]; L% b" Z3 J7 K5 Z1178272 CONCEPT_HDL OTHER Verilog netlist does not include split blocks correctly ! n! W. o: F5 c3 d$ m4 M/ h; N# c- F* k
1190782 FSP FPGA_SUPPORT Support for Altera > 5SGXEA9N2F45 device. 6 c1 y7 b* a( r( h 3 }) _2 J5 Y- Y: \1 h, {1194140 ADW LRM SYNC_PROPERTIES is not resolving issues a based sync_properties settings ! w( Q5 q4 n' X; [ & v& M k, e0 I1195744 APD EDIT_ETCH Diff_Pair routing fails on certain Uvias in the pair. . k* F9 d9 `; ^: N w: m8 ?' S* u3 v. C
1196704 ALLEGRO_EDITOR INTERFACES ENH: During ipc2581 export checkboxes corresponding to ¿Miscellaneous Image Layers¿ should automatically get selected' i1 z6 U& F8 k. t- b; z
0 u. M) f. j5 h% _/ q2 k. s$ u) F0 K1198340 ALLEGRO_EDITOR OTHER Multiple -product option on the Allegro command line does not access the second -product: l! ^% U$ p7 E8 ?5 j
7 B" m7 C t/ @, _; P& w1198596 ALLEGRO_EDITOR INTERFACES When copper thickness is increased for the outer layers, step Viewer does not show correct component position.& h8 a! s# f1 Y# }" J: X
5 @& ?$ m' J% W1199673 PCB_LIBRARIAN OTHER Component Browser fails to load footrpints if they are set with UNC path. g6 c0 v0 s( A9 `
5 M* P' F5 t8 p7 L# q( Y1199889 ALLEGRO_EDITOR DATABASE Allegro crashing with latest hotfix.* t, V2 Z( M* h* I' i
* r2 [$ E/ q4 F, Q5 N9 U
1200303 ALLEGRO_EDITOR GRAPHICS 3D Viewer does not update after changing STEP model mapping 7 e# x: I5 [( B) u4 C$ p; h) F) h( T7 A9 P- m' Y* Z* {
1200449 ALLEGRO_EDITOR REPORTS Allegro crashes when generating Net Loop Report.% [! Z- q* ]8 u* d
. w; k( H: I" E- i1 d1 _
1200915 ALLEGRO_EDITOR DATABASE Reducing accuracy of this specific design crashes Allegro 6 P# T2 v: f* I$ |; k7 ]$ S! @2 ~9 Z6 A6 t6 g+ H1 Y
1201011 ADW COMPONENT_BROWSE Component Browser crashes in DB mode' v, A6 }) F$ r% c. W& N
' y- V/ H" x1 u. P6 f8 I1 ~
1201376 ALLEGRO_EDITOR INTERFACES Allegro hangs when trying to map a specific STEP model to a package drawing.- r6 s" F; _$ V5 G4 B- ^4 n
9 T8 _# h2 P/ B. F( S- M3 T
1201897 SIP_LAYOUT IMPORT_DATA BGA Pin Colors not matching the Colors defined in the Symbol Spreadsheet after updating. 7 }, A6 e" _& F8 `2 E8 h' y0 h# @6 u4 \
1202709 ALLEGRO_EDITOR INTERFACES STEP File generated from Allegro is not overwritten when the variable "set ads_textrevs' F. X% U$ v' x, a2 q4 T
- K! _3 U7 A1 K0 b, d4 ] d b1202820 ALLEGRO_EDITOR INTERFACES Different xml generation for same step model on S106 and S017$ a U4 z' q; i1 b$ K! A) |4 v D
, b. `2 J- M4 |9 _1 a( g" c2 c
1202842 ALLEGRO_EDITOR INTERFACES Step model invisible for one pin dra in allegro 16.6 symbol editor: n" g, P n4 x( h
6 Z/ ^) A" P" a7 r( p1202983 ALLEGRO_EDITOR SHAPE Shape voiding creates DRC with Route Keepout+ ]9 x9 d' c. q$ e* z6 D3 S) f( K
/ T0 m$ X/ ]+ g) I y& B1203125 ALLEGRO_EDITOR OTHER Exporting STEP file with External copper enabled does not show all copper when viewed with Solid Edge or Inventor ' V) @6 V! ?, Y5 d6 ] C# V( P8 u8 F. ?" ~% @2 O' v/ M
1203236 ALLEGRO_EDITOR INTERFACES IPC2581 output with crosshatched shape is not correct$ r- P2 @5 K7 I4 A8 L+ w
% {% X% @ X5 w8 t9 y
1203995 CONCEPT_HDL CHECKPLUS CheckPlus rule, local_signal_no_offpage_body, getting an incorrect failure. 2 y1 x" S0 ?' W `+ R A: T9 | }" s* s3 a! e' `
1204629 ALLEGRO_EDITOR SKILL axlUIDataBrowse crashes the editor or returns error 7 U/ _ d) L8 M0 Y9 a C0 X. D " T4 q1 H, M* l3 r1 |" [1204640 SIP_LAYOUT DIE_EDITOR Concurrent co-design update fails * Q* Q- b; V) s7 v- \" G6 O( G& \" H: v* |
1204881 SIP_LAYOUT BGA_GENERATOR Pin numbers are messed up after deleting a pin at a staggered bga4 F% Q9 q" j5 r- Z" {
# z8 p0 I( }' b% y8 }1204885 CONCEPT_HDL CONSTRAINT_MGR Cant assign discrete models after the wrong model was removed.# ~# ~ m: T1 Q2 Q z# x
) I' `0 {0 P* M1205374 ALLEGRO_EDITOR OTHER pdf out command creates incorrect drill Symbol Characters placement in pdf file when setting film mirrored., [) o. U x+ [; p, L5 X
$ M% C( Y$ j" w
1205729 SIP_LAYOUT DIE_EDITOR update of codesign db fails on exit from die editor + W( W" n4 d$ J6 O1 ?* T6 o: ^5 L" U {6 G6 ]' z3 I
1205801 ALLEGRO_EDITOR OTHER Tool crash when do export IPF.. a0 w. a2 q% ~% B
& }7 S5 t2 z. G8 y7 z: p
1205881 CONSTRAINT_MGR OTHER In CMGR , Objects > Create crashes Allegro ( C" E! F) X& M k9 h4 _* b# T: x# G3 m6 R( S& ~ G
