标题: Cadence 16.6补丁6已发 [打印本页] 作者: dsws 时间: 2013-3-29 16:28 标题: Cadence 16.6补丁6已发 更新内容：7 A( m. C+ _) o, F, o2 \0 B
DATE: 03-29-2013 HOTFIX VERSION: 0061 A- _; o i: c1 @$ r# z- n
=================================================================================================================================== * ^% N7 A( S W" d* TCCRID PRODUCT PRODUCTLEVEL2 TITLE/ n8 f4 u& t( X; W/ l* L
=================================================================================================================================== ; p5 T, i5 L! K2 ~ p v110139 FIRST_ENCOUNTE GUI Error in Save OA Design form / I& b( }; J3 Y625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist. # U4 M* R: d3 p! K642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep! u& G. E/ L$ }% J* j' }3 {' r
650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".) h& |8 V" @7 i$ t$ P- `4 ~
653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend ' S8 |, C9 Y- i+ m; Z4 ^687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect. w2 t/ x7 F% J+ n+ Y2 T4 H: T, _
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics 7 q8 C8 N" H* Z5 _/ f825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other% I# L8 K$ W* B [5 B& E# s5 s8 @
834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming/ ~# x' i o* `# ]& n8 H
835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.2 N$ X0 E! C2 Y1 S( Q; m
868981 SCM SETUP SCM responds slow when trying to browse signal integrity6 N' x$ d- p6 V8 Q. z
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide - M/ {! w+ Z# M. V) c. Z# Y& b873917 CONCEPT_HDL CORE Markers dialog is not refreshed- ^: j1 L% ]2 n
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License 0 I$ Y! |6 d9 q+ w! j* U888290 APD DIE_GENERATOR Die Generation Improvement % Y1 a7 l: J: X9 F; g8 N892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator' a0 g3 Z5 \/ T' |" C/ Z6 t( U6 Y
902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice; t- H% s) [/ i' H
908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM ; H, S* W, U _3 |* F# q `922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols+ ~0 N/ r8 n, a- @1 H
923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences ) N8 V# g) p- h2 Z935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC 6 c) L7 d4 g0 ?+ w8 s. w( p945393 FSP OTHER group contigous pin support enhancement / U, T7 j; g/ E969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database 5 V6 L0 B, W0 V. G9 i( t1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes + I+ R- B2 f! ?! @7 n1005812 F2B BOM bomhdl fails on bigger SCM Projects% H0 d6 N5 w+ B
1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture% e6 y8 t% ^% q& D" h) x! { _: B
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names $ W S) K( M, k7 h1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net. j# [3 ?) u4 d5 S' _, Q" v7 L' G
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical ' ]4 W6 _; l5 @- N1 p. u* C0 `# C0 l1032387 FSP OTHER Pointer to set Mapping file for project based library. 5 C8 i& v/ P) k5 z; l1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 縋LL PLL_3 does not exist in device instance� ) m/ _( S. _+ U& i0 j2 a" E1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart, M/ U; T7 i1 ~" n5 g7 E! w* `
1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding6 e Q o# R! n @4 I- r3 l1 o
1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages. $ W$ i o5 s5 ^0 O+ u+ P3 p1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type ' ~, b x) j9 {! N1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll ~. S4 r/ R- i5 L+ { h1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation 6 w0 j7 j6 k; @2 ~1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects5 T# M1 j2 p+ J _ X8 w$ i
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus 2 S2 C1 |3 d3 t# x1 p1 _) W7 C. m* F; M. k1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts V9 u. C% x/ h9 B( Z
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs- ]# } `$ C1 r$ [3 W# [
1065636 CONCEPT_HDL OTHER Text not visible in published pdf1 |, W; i3 M8 _/ \
1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings # f4 T4 X d: d1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary ' [2 X; C, |- g9 n1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts 4 `- k6 N8 s# D7 D: H! @6 U1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic# v! U$ T8 p& h( S( f$ Z5 l
1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down/ v! _7 G' x! ^% [+ `
1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45 " `7 K; T+ }9 j1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal 3 J ?2 N8 i8 B c$ a* H1 d1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check 1 c$ ]% X, v1 R& R1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design. " y4 _" M# k: ^; U) _1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)7 Z+ Z$ _8 F0 c
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die5 t7 \5 _7 }* W. p7 L
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic : x! s3 R% Q; K6 Z; e7 j1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut $ j) d& k3 B! w4 i$ s, s1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects / Z3 S/ _' u' E/ p1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format , S8 e* v o O# }6 }/ `! `1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net ; m* F0 n9 o, j& U9 x1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic& _8 ?2 W" W) [8 L" M% x3 F
1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible ; ?5 ~! `' Z( c6 _/ M' @& ]# v1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars. 9 s [4 T% b* u- h1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.$ ^2 W( b) N$ l5 D; m* n
1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors% T2 s2 ]9 J8 R3 D& a7 m
1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.8 C G2 U% M. E3 a* F* h6 v
1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition & S1 f( E- E7 e, w1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor # q; c6 b+ z4 }% D1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options 2 \9 Z5 {3 B/ s9 @% @1 D; ^' D+ O1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5. h+ G7 z% l! R# {" Z& d6 I: t
1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.4 w+ {. h5 h8 Q; a3 T
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate( m4 j9 J! b& U* I' m. Z. t, U9 K4 v
1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3 ! T' F4 _6 h, Q9 ?1078270 SCM UI Physical net is not unique or not valid, x5 N7 U: _7 i8 q- A
1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted: r% U. H3 a7 Y( V- ^
1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle3 t8 D4 i6 h3 h3 [) Q0 f9 [
1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs9 u+ ]/ K9 ?: c4 P0 F
1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage" ( W) i; p9 }- g0 x1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters) ^+ v! O r# _" d$ E
1080336 CONCEPT_HDL CORE Backannotation error message ehnancement5 I! M+ D! U2 t
1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license 4 f% w# J) \/ q& M4 I1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd5 n4 V% |0 u: S, X
1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error- W+ ?* ?& t- a, {, P7 h, X
1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated." [ V; ^: i. c _/ ~7 V
1081760 FSP CONFIG_SETTINGS Content of 縁PGA Input/Output Onchip termination� columns resets after update csv command6 [, _3 t/ w+ \3 a! q
1082220 FLOWS OTHER Error SPCOCV-353; u! l. u: B( e' k, \6 x+ t
1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.! }+ W+ Q' y7 L# I* o# b& K6 L
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command! q/ n7 O. x% u# p2 }
1082737 CAPTURE GENERAL The 緼rea select� icon shows wrong icon in Capture canvas. ( Z2 |* M: L* ?8 G1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name; a& N$ F G8 ?' s, p/ D! V9 H9 v
1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way8 X6 `2 H0 W7 U9 ]) [! H, |- Z
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher ) m3 s& }, q% o7 b4 C1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI* i2 h6 Z: i4 T# W4 U. c; G
1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file 2 q- o- c0 ^; t& [1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.8 [1 q) |+ T2 }% F @8 P
1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates1 }" x* J! |" v1 n
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters / t- a) e6 p4 p: q) `1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes. $ E; |) x, _5 s8 d: M" H' W1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results / h* `2 w8 J$ ]( i5 I: F: s$ U; V1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.' Q1 M# c; D! d/ ]1 H$ W# Y3 n
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update" n4 |# J3 c: z2 D% L$ y
1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO 5 U1 e2 h1 o" `" s# Q1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working7 k; j! e# r5 l+ m3 S% C
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules. 9 r m: B0 x0 m+ E1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design ) l9 ?5 Y* [/ M% k1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated) ~2 {, q. C5 \& M" a: k7 E1 |
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins H7 Q0 E" ]( y) S+ K
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity / i1 m+ p! J# _2 g1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.2 F1 J& r1 k6 W* f% x b5 B6 l/ F! ^. K
1087221 CONCEPT_HDL OTHER Part manager could not update any parts.6 i. \8 D( u1 R5 L- i1 o# d) T
1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space ! n4 o. D3 L# R% V1087295 SIP_LAYOUT EXPORT_DATA Enable "Package Overlay File for IC" for concurrent co-design dies too0 y) p6 H! {5 E# b
1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice& q% l3 ~7 g1 L8 |" a
1088231 F2B PACKAGERXL Design fails to package in 16.5 / ~0 {4 V6 _+ I# z) H# D2 w1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.: N0 a' q% @' n' R5 z
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor H; h z9 L% L) v* Y3 P1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager ( e7 Z4 x) I7 t0 h1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling? - t I. w3 Y/ d& P. k+ t* p1089259 SCM IMPORTS Cannot import block into ASA design 6 @" X7 X7 ?. Z- E* m) ]1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form6 V3 G3 S0 ~: |$ J( Q3 G
1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project" J) m) F! ~5 n. Z: K" g
1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory 8 K; p3 y, O/ x7 }. X- x" O& F1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.5 k3 O9 Z& J3 ~: G7 z/ Q
1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165 7 s) | ?' C$ o; `: y7 i7 T* H1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.( a; R+ f$ S" B- m
1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22 7 ^4 C$ u4 T/ ~9 r9 W" y; K, X1 P! `6 _1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.( Y% v1 v; N. p0 m7 U ~
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.7 W& a; B: U! e3 r- r$ K+ U
1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled3 K2 V/ T! {, K! g7 F/ E0 O# y
1091359 CAPTURE GENERAL Toolbar Customization missing description3 U1 [: A7 P+ b. @) t/ m
1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive2 b) I- g, g* [1 \
1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time9 v# |* o8 H, t- P
1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5 ; ^5 ^' c9 h/ Z, M& a+ q" s1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design + G5 |- Y1 Z& y4 B/ j& I9 L1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled; p4 X! ]( \4 b5 I ?2 U2 [
1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters7 q& J" q( i0 G: r9 v" e
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error+ C$ }) j! |! i: @: K
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder 3 K! M( E1 p2 N! K9 j1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor' v7 \/ V& y8 `+ ?* S; n
1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.# y k" k* I% w1 n0 m. u
1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time , h ~5 C! z5 Q- r% T# O" t1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.) s. R% h) R6 | M: }/ w" P# Z
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible? 8 z5 z# X! a$ b1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic7 S9 \( S6 y ^! G( x8 M
1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5) i T5 Y2 L$ l) C3 f
1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet ; v; X& u/ x9 R" X. S4 x' f' {1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die 1 {8 T3 V) w; e7 M4 Z1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block7 ~' n0 B: Z% v7 Z1 G+ X7 k
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3 ( w2 ]' _. B6 S$ b. l7 J1095861 F2B BOM Using Upper-case Input produces incorrect BOM results 8 g& \' O, J( K- K* P7 j+ J. c1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import 9 i Z! Q( ?5 D$ D: h1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically7 u; X% `& o- ]0 {. g
1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias; f; J! T; |) D: y3 r
1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate$ \1 M" ?8 J* n! d
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors 2 w) ~5 g1 @9 S1 D8 V* E) L1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL- _) H- X: r: |* C' T3 c" y% Q
1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly. - u: O7 u" ^: a# m5 l1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side z! b' a0 N1 O1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command - H2 S, I" Z2 H1 @1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.3 _6 W: [+ c7 L/ _4 U: v- s
1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives% g) v2 [3 Z4 D; |6 \1 k K
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork - X1 G: i% V) M, W }1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts4 x2 t4 D" z0 @ `, E( s
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy 9 h5 x7 J8 B& N& ~1 X" u1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.! `# O. E6 v3 A3 X5 M6 n
1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties& x) D4 q9 B5 o# _
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6( r, L6 z8 j2 v
1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad 3 f' k G+ U+ [6 c+ G+ H. l1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3 q$ ~& X, o9 r2 ^# X" K/ E$ B9 [1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad- n: v* Y3 X. y8 X
1103703 F2B DESIGNSYNC Toolcrash with Design Differences' ~; p; i e$ p9 d$ p( N, n1 q
1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view ) f0 {2 W8 W$ v3 z1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6 4 F, G4 J0 z) T. F1104121 PSPICE AA_OPT 縋arameter Selection� window not showing all the components : on WinXP6 K2 f* c6 v4 E C* ~
1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly + f. t% z# S( h1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM# T* V- I3 l9 j; o
1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule. , x. _9 f9 s% Q$ W1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires. 4 _$ S" j; z' N1 Q4 v1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form 4 N [9 k% b& s* c& Y* L. F! B1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part: ]0 _% ~9 k% k+ o9 q, ^6 K) r3 b6 I" t
1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked + ]( J$ K0 n; e$ F4 F* T* ?1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax $ A! T" `" j, L1 h$ T) _: M4 _1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6& T" i; w4 e2 S. k; _9 |; `- E8 p5 ?
1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only) w$ V( A' b' a; S" U
1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid % G! e- t7 o5 y/ x4 R1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support. / f6 z' L1 C; @4 L1 U8 T" l1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param% y- A3 M0 x. [2 f
1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish* N) |+ I. c5 [% H! |. B, x
1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).8 ~0 P4 Z% L3 o* l* b9 L
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke9 q* ]- k) d, O7 X- `1 g \9 _+ u) J
1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.2 E* N) ^ n1 {" l2 G9 Q* v
1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode % ^. v- u" d3 M( ]: i# o4 B1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs " z: g) }) m0 v1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6 7 C% a8 {- B( J4 ~; Z9 P4 i1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins. # I/ ~* j& |3 |$ ^1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON 8 d2 s4 |- b. W# x( y1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6 # }1 ~5 i4 @9 g$ A1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset % Q8 B6 }3 u; [2 D, P& n1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters* }* C5 M5 p. \) {, y4 E' C Z3 B1 A
1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend( s5 E- P& Q; l; K9 o6 f4 r( M
1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP6 d; s' U9 P" o2 z5 r- M0 ~
1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint$ v& K. h# I+ z4 @) b. }3 r
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan * a0 Z6 V% O% e1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color. 8 W: k5 }6 C/ s+ _+ B1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file - M3 ^9 H y2 v) A1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6 ' w8 n0 y$ [& L ' o: D! |) T: ?# i: |. gDATE: 03-7-2013 HOTFIX VERSION: 005 * L8 W# ]& d I# o0 A: g, P===================================================================================================================================2 @' s6 I4 @9 @4 |5 w% ?
CCRID PRODUCT PRODUCTLEVEL2 TITLE - n0 i' g- h! O1 C6 M$ \. u! C$ T( c1 C% z=================================================================================================================================== + u e6 N9 K5 a: l! U& ^1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 1102 4 Q2 s6 v; f. a) v# }, J3 V, o% _% u1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed! S$ O5 N6 E& O& B. [, L* B$ K
1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently 7 e' ?: f& p) M& v1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind 9 |; h% B6 Z- K0 H) D0 x1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view 9 X0 ^! S. P `3 A1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed' ]) p6 W$ I1 }5 V
1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM $ J! O, M2 k0 D8 U/ T: W1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.6 1 Q/ P, Y( H$ D" B1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement. 0 ^3 e: q! z6 Q" m m2 k1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design7 P- H# a; p- S( p: x
1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional$ d' v9 _; d1 J i2 V
3 b7 b5 o) T) U5 F' H& A* jDATE: 02-22-2013 HOTFIX VERSION: 004 3 o5 N2 s# q+ S1 K. w" r=================================================================================================================================== 3 O' T/ g) e/ o1 ? u' w- D2 [CCRID PRODUCT PRODUCTLEVEL2 TITLE* P! F2 r' }! g4 Q' V; t
=================================================================================================================================== , O, S8 n$ n. l+ m7 _9 X: a1081026 ALLEGRO_EDITOR GRAPHICS 3D Viewer do not show the height for the embedded component correctly & }7 G! ] ?$ n% o1095225 ALLEGRO_EDITOR EDIT_ETCH The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing + a' w& U* `' ~1096356 ALLEGRO_EDITOR DATABASE Cannot Analyze a Matched Group in CM 1 v! E. i+ |; P: I- c1097481 ALLEGRO_EDITOR INTERACTIV Allow replace padstack command in design partition: j/ g2 Z7 w: t0 L0 |
1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend ( o5 R9 x4 c* s1 K) i. W, k2 c1099958 ALLEGRO_EDITOR PAD_EDITOR Library Drill Report producing an empty report & ]4 v( B: D9 l! B' [1 z1100401 ALLEGRO_EDITOR OTHER Invalid switch message for "m" for a2dxf command9 z! S9 {( |" L; r
1101026 ALLEGRO_EDITOR OTHER utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit. - N$ t6 s2 A, S1101064 SIP_LAYOUT SHAPE 'Shape force update creates a rat7 Y$ Y Q4 v, L7 m8 s {
1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated.$ T/ z; h% k9 m t
8 n( ^: ?5 \' V$ ^* P1 G/ q5 b% z
DATE: 02-8-2013 HOTFIX VERSION: 003 Y* B R) E- G; a+ R7 b+ k" _9 B===================================================================================================================================! D7 R7 Q3 z7 [
CCRID PRODUCT PRODUCTLEVEL2 TITLE 7 T0 j$ }) v' Q" P5 Y===================================================================================================================================9 J4 D2 W6 {" R& p$ ^) s( t0 d
1077728 APD EXTRACT Extracta.exe generate the incorrect result' u3 V8 v" m" ~0 \, b, d/ d
1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF0 U/ u! g ^+ x8 S9 D- a
1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer $ b% w/ U, H8 ]4 l% m |# D% l1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing. - e. A6 l& d8 u2 q7 f4 E# ~: N1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on ; G* R. O% V6 e j# R# f1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent( W+ ^9 B. z" Z; ^9 [
1094788 SIP_LAYOUT WIREBOND Wirebond edit move command # \' a+ w& A6 Z$ n1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor; S7 O9 e9 E7 W& B4 X; X: X( z& ?3 B: v
1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn縯 show up after 縎uppress unconnected pads� option. ! B4 `1 o7 o; L3 e- |* |1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff 3 G) |5 X3 ]1 K' c6 x* ]- I3 z1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible z0 G! Q. F4 b9 U% R
1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35 ; K' Z1 @4 x4 B4 {9 H1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.2 H$ ]( F( d% x: d8 ]
1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes. ! j9 g2 z, Z% i7 q3 E2 r9 Q1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license. ' A) k! B. F% n 2 j5 o% p+ t; m& Y2 m7 G. f7 }DATE: 1-25-2013 HOTFIX VERSION: 002- K2 @4 _0 [3 y4 O- {# e
===================================================================================================================================9 t3 I# K0 h1 `) X9 Y+ n. N
CCRID PRODUCT PRODUCTLEVEL2 TITLE 4 @$ N. d! @( j2 s" L===================================================================================================================================! l$ l6 h! e2 t J1 \
491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute( P$ g+ k, G! O+ W' J% F6 ]7 o( Q
863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc" - B- U" k6 y$ F8 J, k T! A' R4 k1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes2 F! W* D v6 R. `+ L9 S7 {$ t
1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable 1 f6 l6 j* E7 e% `1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33 % L7 _: g$ W( E- p- I1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence 7 Z) O( N! C _% p. S2 r1 l# Q! J8 C1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator' T$ t6 g1 _8 |, v$ q( j! F
1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command4 s" x# X8 p8 U% c" F8 c3 _
1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.6" ?% j* q# a; y2 Z% [
1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note. + A% U% f$ b6 O+ E6 _ {1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.9 O# i; j1 G' ^5 f; R
1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL.! W e; b' {2 {
1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0 # `' K! l* w( G* x8 X/ @1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white . r. E/ y1 C& `. n/ D5 T2 S1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure3 d: W+ c* Y' J: K
1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer ; a' r+ N8 z8 T+ T M2 m% h/ k' c0 V1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile. z1 V6 x7 s' d
1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.: O# i& `' Z2 m: }
1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name.# H* a0 i$ ^* e& f( x" B
1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.6% i; @4 D7 _0 C# B( W
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout 6 J3 j# p, U* a( | q7 q8 k8 G" @7 T1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file& x7 [4 y n1 }' a
1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing., a: B6 J2 h* a& E
1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.' J) @3 D; \* w6 d# E* }
1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties 1 R; X/ `6 A/ A9 w+ _- f1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error. x8 m, h+ B; T
1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric 0 {. A+ s/ u ~4 E9 Z) Q1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol. ( D- p/ X2 s& f) s) v1 }1 X9 W1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue! m8 J9 h6 a( I; E
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command * P5 ^3 m% g5 J& P9 d1 @1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled, W1 ?- t, ?& o: C* {% g
1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error 3 ~& t, r) @" [- ?1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled.1 a2 o e8 p0 `; u, \3 b
1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function# r7 [* N; y6 i3 M+ O: N9 S8 v4 e6 ^& q
1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command.$ K1 i# T- i0 [. ], M5 n( O4 d
1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames? # I) O7 W( n7 I, i" e$ f* R1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group$ ~& E4 r4 C) W0 n. |
1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle . @/ d# C4 O) {4 }& \- z1090689 ADW LRM LRM: Unable to select any Row regardless of Status% }' l/ g. F* o. `8 k
1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle1 P* N# D9 C0 J( h* t
1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas. : k. B: w2 v' z0 o- M1091218 ADW LRM LRM is not worked for the block design of included project q/ w5 Y4 Z0 M6 g& D6 P: [
1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads" D6 e9 J; @/ J3 R+ G6 y
1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width9 R) C/ }) A* f. Q; N T. i
1092916 CAPTURE OTHER Capture crash' u: i/ r( z, h* I: T; g
1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database) S' p1 N* M. ]' Y! ~! Z9 D+ |" o. S: Z
2 w% w0 g U" p; s) J& k" ~
DATE: 12-18-2012 HOTFIX VERSION: 001 , v# J( S3 @5 G" I5 B+ y7 E7 }===================================================================================================================================9 O. G& ]( d2 T* X- ^+ y
CCRID PRODUCT PRODUCTLEVEL2 TITLE3 o. n, Z' _" `# ~, m
=================================================================================================================================== C, |7 G& g7 N3 v. I/ W501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap. r, p1 `* ^, S1 y: }& s& P
745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched/ \, e: `, ]/ e6 z# Z
825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted; I+ r- ]- c- [& R
871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash( h& z% A( y" r* p9 O/ b3 z
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments, z3 W% L! \1 {: \8 Z
898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore # J6 L# X8 x5 R. Z( U923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties! [8 ]$ e/ n) B5 |
938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic/ i4 a* |: B2 M2 H
947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape. : X2 e& `3 S" I: ^2 E968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing" l% ?! ^4 v1 Z8 Z; N
976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor " ~) ]9 g4 n, u981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.. r9 G' p$ P1 ^' J/ l
982273 SCM OTHER Package radio button is grayed out3 {+ j5 M, d# C4 ]
988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command. a& U+ _. N, ^, f3 k
989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode 0 b# x/ P3 F& ~* D$ L8 I5 E993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).5 q3 [# P; ^7 X
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections 9 _% z% a Y& d: M1 H997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used? : E1 @1 f$ v0 ^( T" Q; e% I4 ]4 l3 j1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model 8 @+ D$ d, A" p0 y7 E$ K7 Q3 w6 W1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs & {- h. S9 |- V6 W, P1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg; B7 {; L7 ~3 {3 [5 J
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints. # j' |& W/ s Y% c# K7 Z5 L7 V1016859 SCM REPORTS dsreportgen exits with %errorlevel% l ?& J8 A+ V& p1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin/ c, q+ p1 T* X3 Z5 V9 O# _
1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs & V. O0 h- s8 `/ t8 g3 q9 K! s1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts 4 O. Y; @4 n' E& z2 N1 |* }1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140 2 }$ `3 K) w# b9 Z. e/ w5 `, A3 o. i1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.1 X4 S; k. |( h- W
1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button - M f8 p1 P! Y0 ~4 M1 U1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out ) D3 h8 i4 r$ c7 _# n6 `% \6 l1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist: R, k1 a5 ]; b8 S/ o/ D6 m
1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed8 {$ @ {* [& \5 j) h/ Y
1035624 CONCEPT_HDL CORE Options pre-selected when launching base product7 y* |+ @( z* x9 g
1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly3 C3 \0 T% I. V6 n) E8 ^( E
1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it. L% H6 Q7 T) R) y
1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file) 8 U2 y, ~" C* x6 ?- a1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol. V% [ u" J) _) x, G( m
1038285 SCM UI Restore the option to launch DE-HDL after schgen.5 R' }; o j8 o/ f
1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."& |6 w1 ~% x# B% K$ y
1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro 6 J. e% O& f9 w3 @/ N9 J" p {# v1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected2 I- W# q) p, K/ c
1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing, e; ]; A! d9 ?' c
1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.* L4 C3 r, i" z/ U! A
1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.' n. F: v3 D! j" C4 n7 N K( X
1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu , q- Q" s; H1 `% D% s Z1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.( O9 U2 C5 g; \! C
1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow 5 `8 w: n- x) c1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory6 f. U' ]4 k6 `1 i3 ?
1043903 GRE GLOBAL This design crashes during planning phases in GRE.: z/ f7 \8 U* F% x& @3 N$ v8 B. n
1044029 PSPICE ENCRYPTION Encrypted lib not working for attached : m3 o- O6 {' X1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory 4 N& S4 b1 i4 C# u `. A1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.4 S7 M P1 z. i1 l P: M
1044577 GRE CORE Plan > Topological either crashes or hangs GRE) U/ j) Y! g& A/ O
1044687 TDA CORE tda does not get launched if java is not installed8 O0 G: M5 p% b, z. J r+ ]
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die2 S4 e0 l0 z8 o9 V3 s2 O
1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form. - g- u+ B( q# O1 L; x, B5 S1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board? ' ~7 y I0 m- q1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51. ; K! X$ j# n. {4 Y, q4 l; M' G1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry. 2 [0 k7 |- I: Z- D1 E! z* z1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow ) Y! Q! ?1 M2 m1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.5 n7 o9 N/ @5 V) a
1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill* _! K% Q4 V/ |( t
1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.. i$ N$ v/ X* D: j
1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5 2 w6 o% w/ V& G2 \4 I% [1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5 ' y# ^0 p1 Y6 A" G. j1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value 2 q2 n6 Y7 \+ A. p* D" V1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version+ S) ~0 c+ R0 z3 @
1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯. ! X* [1 C/ I4 ^8 e1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.8 G; U6 M' f" @- E4 C) s
1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.) h2 C+ \4 [& y& n/ ~
1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes ( a+ t' k1 m x5 P, l2 p' Q1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.; b& q9 ]: n9 p* f- P; T) t
1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3/ ^* ~8 Z" U1 Y2 ^0 t* k
1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file; r* ~9 [3 |0 ~( N6 l1 J# M/ s, _' h( `
1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors5 v# N- w0 s$ F) w& {3 k
1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated. 3 W7 P& D# |5 |& y1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts. , }5 y; m) W. W. i8 l1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design4 m( D9 m2 K2 w# B+ E- B; D
1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs( w, k% m5 i" S o
1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label1 {0 q0 H* D+ {- Y' P# N0 {- L) Y
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction. ; E6 F" `# ^( Z! T9 m+ a1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy! U' v% m b2 @' q1 D- r
1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down 2 m9 F4 ^/ | U( }% e4 |1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection! y, j6 d( D, u* k% N" p* B8 i8 L
1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.3 N- ^+ L/ ~+ Z+ X# o: @
1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views/ z. y! C1 Y0 M$ E! {7 {9 B
1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline 6 U1 u* O9 c* @8 w. u6 c: K. r' h4 ~1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design. & ^8 }" v% a9 q1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created.5 w' i/ u+ |" U$ d# Q1 ]& S7 L0 k/ \3 v
1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move / P8 C! g) n5 x, _1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value ) ~$ C* u9 `+ i( t7 t& a2 r1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer5 I9 k l t. I1 n
1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report $ z. i9 l! h! V1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.. Q1 _& D; n. p2 g( q
1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete1 g; }4 R5 o9 w0 |
1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties. : A7 B, k! R4 M- U6 o. ]' |8 b1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets 7 v8 j, r1 f' v1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?; C7 d+ k: R* a/ |( V0 Z' h7 P
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values. 1 O/ j3 A; d* k$ V$ S1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished. , z, k& ]* z9 _1 I7 c1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00 4 b- w8 x" C( N J6 p& M1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation( o! i2 s) d# S5 ?0 Q! P' f
1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed. ( R! J6 T4 e0 D+ d1063284 PCB_LIBRARIAN OTHER PDV Save As is broken ( y$ [$ w5 k/ C4 p$ d) I9 m1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs # ?8 S. W; n% C- {4 U3 Y2 h1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.4 ]' K" ~ H7 R
1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager. : ?5 D0 C0 ]( H& E$ \/ T E K1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design # ^0 F- E& b8 t2 Z1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV , e F& E( `7 k- c1 d6 J/ `: o1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green. / l4 z/ \( m% P! ?6 ?$ U1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X+ H& h. R/ w8 W( h1 I- {
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application / b5 s; s) f# Y- |) W& r1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report ; k [+ O m2 L, i1 O! z1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC* }4 G( ~ [9 a I& j" q1 b& q
1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic : [+ F' ? h1 K( r5 _, p1 k1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent. ?. D8 z6 H, H; l
1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file / l& `% ?2 A+ {# ^& w* L1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command7 m7 K8 `' a4 \! Z
1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended9 E' {3 q/ u! s* B8 h. \% r
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067 " l4 ^9 @% G+ c& i6 k, A1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design8 P* F/ Z5 X. P* F: _
1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify U& o, k! }! `) k1 u1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids' l; H) {! X2 c# @3 _; ]
1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes ' x" t3 A8 m8 `) T% x, c! k. h1 g3 a1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow8 N7 i9 Q# O3 F% f% D
1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal S2 B! W5 a- R9 l6 \+ z1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.2 Y9 _4 _% G% r8 {( X. U; j4 m
1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6 % M8 f7 ^ Z4 R) Q6 U/ L1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5 5 X2 O* z; w) e; {1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode. 1 O" l' u; j7 \3 |( `7 g% k6 h [" P1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.7 c3 j# w4 \( I U" _- p
1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor# d" C3 N2 [! C+ i) ?
1073464 SCM SCHGEN Schgen never completes. 9 h, x' S' }% l5 k6 f1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory ! X4 M. A8 s% g1073745 CONCEPT_HDL CORE Import design fails * f1 z7 m4 f* b$ o) a8 _0 X) v1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'" w: J c, V7 S" y
1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE$ n. l, Q. d. }2 `8 q& s
1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist9 p0 ]' s+ @/ N0 e g8 V8 i
1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter L- r& p! ^0 c, [; `. H
1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal x( g x" ~( W+ ?2 z) X
1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data. 2 M/ {" K7 \. a" |& ^* y" j1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI ; | P9 L3 W6 V2 G+ }4 K' ?1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block) s" I0 Y' \. x0 v' a; Z
1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer 1 I2 n1 o* P9 C: e) p1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces 1 K4 H: o: o2 Y" i/ m+ z7 v h1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2 . U# g% H3 O# g# @" ^1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix b$ n1 q1 [$ x: _1 _/ [9 e
1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes) @% |3 {' ^' M' U& L' F# C s; O
1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top6 r3 J2 _1 N9 t6 G5 u$ I
1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas./ ~8 S0 E8 r7 Q' L3 I
1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value& C5 S X# Z. \, k" e7 T( }; ?8 O
1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.63 X& f- B8 a6 H( j% @: ~9 I! T5 Q
1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey ' M3 H" h; w% e4 \2 f9 g1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database 8 y! I9 a& F! l1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset7 T4 V) R, H( L! P7 d& g2 Y! G, d
1077169 APD SHAPE Shape > Check is producing bogus results. d2 K3 [- e* ~% s! U G/ T
1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board.5 N. B8 v5 ~$ Y3 X. ?: x
1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim 7 S6 @! T5 y+ i* k4 R1078380 SCM OTHER Custom template works in Windows but not Linux' |1 _5 W9 v8 v1 y; B5 c4 ?
1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.' D3 M" T' a4 w
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide( D( W& {1 ^* B y) f8 S+ }+ j
1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping' r8 H$ a S, t& v# G
1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match" , C" B5 E2 y; s# d3 s3 S2 U2 b2 j1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text' U4 x: m" |, i
1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control1 n* L# x8 M7 W" ?/ Z; d
1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical.8 f8 H' @& w2 i3 B7 F {3 d' p
1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.' V( B P4 ?1 @, L( W+ B
