) J5 D7 t2 U! w" T # H5 ?& U Y# ^5 G, FSolder Mask - A green layer of Solder Resist is coated on the external layers of a PCB to prevent the copper from oxidizing when exposed to air for a long period of time. The Solder Mask is the opening that exposes the Pad for Soldering, preventing the solder from flooding the adjoining copper. 7 O) ~3 ^0 f/ M. w; q Pad - Through Hole Pad has large hole and is used for mounting and soldering Leaded Components to the board. Via pad is usually smaller as it is only used for inter-layer connection. Surface Mount Devices, the pad does not have a hole in it. T- I0 N0 c t- T3 A
Solder Paste Mask - Solder Paste are used only on Surface Mount Devices, the paste is made up of tin and silver alloy which is printed on Component Pads by pressing it over the Solder Paste Mask. It melts into liquid form when passing through a Reflow Machine and solidifies as it cools attaching the pins of the component on to the pads. ; T/ d# O! v5 ]4 v: f& A0 qPlated Through - The Plated Through Hole is used for inter-layer connections, linking the electrical Hole signals from one layer to another by plating the walls of the hole with metallic alloy. The Through Hole Pads and Vias in multiple layer designs have plated through holes. The plating also serves to improve mounting strength for Leaded Component. ! o" K; }4 M5 O; `4 ERelief Connection - To prevent the heat from leaking too fast from the pad to the plane, creating Cold Joints, Air Gaps are introduced. The resulting Relief Connections are used for connecting the copper plane to the pad or via having the same Net. Plane Clearance - As a Plane is almost all copper, any Via or Through Hole Pad introduced that belongs to a different Net will certainly be shorted to it. To prevent this, an Anti-Pad or a cut out must be made to allow clearance for the hole to go through without touching any part of the Plane.
作者: changxk0375 时间: 2007-10-18 16:42
提示: 作者被禁止或删除 内容自动屏蔽作者: tianhao 时间: 2007-10-18 17:27
一步到位！！！作者: superlish 时间: 2007-10-18 21:13
顶！没啥好说的！作者: 309007 时间: 2007-10-23 08:16
顶l作者: coco 时间: 2007-11-12 10:56 标题: 不错 俺也顶一下,因为焊盘描述的太形象啦!作者: droden 时间: 2007-11-16 13:09
好帖！！太形象生动了，我一直都在琢磨这个问题作者: killerljj 时间: 2007-11-16 16:09
good！4 o5 \1 Z" T( n
以上两位老兄能否提供下资料来源以供兄弟们参考？ $ Z! V* P: c$ H' S5 Q& p4 D, i% v e谢谢！！！！) {; F4 O" x* ~. l, L: c4 O
$ `5 T; Y6 y% @ U) Z
[ 本帖最后由 killerljj 于 2007-11-21 20:55 编辑 ]作者: killerljj 时间: 2007-11-21 20:49
偶也跟一贴！ - O' R3 N M u以下内容来自《high speed digital system design》。. ]+ n& `: n" U2 u
3 g& Y1 K$ X1 `0 |7 ?
A via is a small hole drilled through a PCB that is used to make connections between various$ {1 u( [- c: b% e
layers of the PCB or to connect components to traces. It consists of the barrel, the pad, and : O1 d4 X5 E3 D* y, X# wthe antipad. The barrel is a conductive material that fills the hole to allow an electrical* m- H! v% m5 [5 \( V: T
connection between layers, the pad is used to connect the barrel to the component or trace, x3 L7 ~# ^8 f9 o0 |% K8 f0 E5 ]. e3 Hand the antipad is a clearance hole between the pad and the metal on a layer to which no4 O2 U* r3 @9 O
connection is required. The most common type of via is called a through-hole via because it7 p" g/ w1 E/ R' S
is made by drilling a hole through the board, filling it with solder, and making connections on ! x, A1 h: L4 F5 sappropriate layers via the pad. Other, less common types of vias, used primarily in multichip! _7 e! b ]& N
modules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts 1 @& L) ~/ Z: g9 w7 ~8 `a typical through-hole via and its equivalent circuit. Notice that the pads used to connect the 9 p" R3 X, S( F- u0 R' Utraces on layers 1 and 2 make contact with the barrel and that there is no connection on+ I8 e! I- w2 |. j. S
layer 3. Blind and buried vias have a slightly different construction. Since through-hole vias+ S5 r; n4 p2 l5 C
are by far the most common used in industry, they are the focus of this discussion.- B; o' j b# F: q
1 H* P4 V; X3 K- o: UNotice that the via model is simply a pi network. The capacitors represent the via pad 8 X0 H6 ]& O: A6 V: x: X$ R* N& A, acapacitance on layers 1 and 2. The series inductance represents the barrel. Since the via! \ b8 I; S Q; R" K- N
structures are so small, they can be modeled as lumped elements. This assumption, of ' j9 X& u! `8 kcourse, will break down when the delay of the via is larger than one-tenth of the edge rate.% \1 w2 d9 T6 F2 g; ]
The main effect that via capacitance has on a signal is that it will slow down the signal edge, E2 W# @. Y5 X. d, \1 ? v9 k' a
rate, especially after several transitions. The amount that the signal edge rate will be slowed 4 E. ]+ s/ ~8 b" Q+ kcan be estimated by examining the degradation of a signal transmitted through a capacitive & V) ^) f. G% K6 g7 e5 M1 Xload, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive * I/ o* q' T4 {8 T" L2 f# Xvias are placed in close proximity to one another, it will lower the effective characteristic5 d6 o9 i1 F2 h V2 J2 W
impedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is" b) q( _! B7 [- L% R9 A
[Johnson and Graham, 1993]
俺也顶一下,因为焊盘描述的太形象啦!
{96FC0D4C-0660-4EAF-997D-86052CF147EC}.gif (30.82 KB)
