标题: 这个层次原理图为啥总报错呢？ [打印本页] 作者: winz 时间: 2011-8-17 17:00 标题: 这个层次原理图为啥总报错呢？ 尝试画个层次原理图，很简单，就几个电阻一连，可是画完了DRC的时候总是报错：; r; N* l3 W" s
Checking Misleading Tap connection 9 v- Q% S6 n& @$ ^ERROR [DRC0039] Tap may not be connected with the bus Check Entire net. DD1: SCHEMATIC1, top (3.55, 2.30)3 W2 [9 x1 d' K3 R5 V* ?( h! Y7 b' _
ERROR [DRC0039] Tap may not be connected with the bus Check Entire net. DD2: SCHEMATIC1, top (3.55, 2.30) ! G' a" Z- h6 P6 U+ N: I/ D4 ?ERROR [DRC0039] Tap may not be connected with the bus Check Entire net. DD3: SCHEMATIC1, top (3.55, 2.30) ! `9 j3 u8 r% K2 m% ~ERROR [DRC0039] Tap may not be connected with the bus Check Entire net. DD4: SCHEMATIC1, top (3.55, 2.30)1 c8 E: M; _/ V, F% I! \, s9 V
hierarchical pin name D[1..4],; A: C" \5 V7 {" v
bus name DD[1..4],2 b0 V4 y- k! K' ?- _8 i3 B
net alias 分别为DD1，DD2，DD3，DD4。 ! N% X, y! i: B- M6 m问题出在哪呢？如果把根图上的bus name 去掉，就又报警了， # U8 q2 \- x d( y. I6 m" mCheck Bus width mismatch" n" A6 ` |7 M- ~3 Q1 S3 k
N06946 has not connected with proper width& G2 G9 V9 o" l9 l8 \% W4 k! S& C
WARNING [DRC0030] Bus width is not matching with the port Width block1,DD[1..4]: SCHEMATIC1, top (2.45, 2.30) 9 f$ [0 i `: bN06946 has not connected with proper width0 @) }9 q& w! ~' D( ^1 m
WARNING [DRC0030] Bus width is not matching with the port Width block2,DD[1..4]: SCHEMATIC1, top (3.55, 2.30) h1 m6 m; c6 g
D[1..4],; A: C" \5 V7 {" v
