Hotfix_SPB16.50.002出来了，哪位大侠出手上传？

cxyjoe

Hotfix_SPB16.50.002出来了，哪位大侠出手上传？
6 ^' S" F8 p5 Q8 F  ahttp://www.nordcad.dk/dk/teknik__service/downloads/orcad_allegro_software_opdatering.htm

MentorUser

Hey!! Thank you for the news!!!

amaryllis

补丁出的好快

penny190

又出囉～～真是快阿

mengshang

等待着下载

interrupt

还会不会异常退出啊

biglin

咳..太快了..

rx_78gp02a

期待，最近遇到铺铜的bug，希望能解决

foxconnwj

DATE: 07-24-2011   HOTFIX VERSION: 002
===================================================================================================================================
  {% j: M- N8 f1 f5 `! M: vCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
. l& [" f# ]2 q0 t$ d) y===================================================================================================================================
527444  ALLEGRO_EDITOR EDIT_ETCH        Slide command needs to be enhanced for same net spacings
583257  ALLEGRO_EDITOR EDIT_ETCH        Add Connect and slide command needs to be enhanced for same net spacings.
+ `# q; B/ B8 e3 n$ `4 H$ l# o4 A  y3 Y592956  ALLEGRO_EDITOR EDIT_ETCH        Same net traces will not push and/or shove each other.
, W, `( t/ Z0 h& Y, j) V9 R1 _745285  ALLEGRO_EDITOR EDIT_ETCH        Requesting a true "shove" in Route > Slide for Same net routing.
1 A0 \& A% _3 R1 m. p& d+ q773503  CAPTURE        OTHER            Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.
! Q4 w0 s1 D4 ^1 E774270  F2B            PACKAGERXL       Require to ignore space in Pattern setting to prevent duplicated Refdes.
799984  ALLEGRO_EDITOR INTERACTIV       Enhance the Fix command to select just cline segs
' d) [# V. }, c: c809008  CAPTURE        SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
810058  CAPTURE        SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
. I" i) U4 T7 ~# l4 C! m" s  |, |821133  ALLEGRO_EDITOR MANUFACT         Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format
7 X( X$ Y) B9 ~3 _; I. m6 T831710  CAPTURE        SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
842410  ALLEGRO_EDITOR EDIT_ETCH        Ability to slide with "Shove" for "Same Net" segments/vias.
854971  ALLEGRO_EDITOR INTERACTIV       Capability to add cline segment in a temp group
860772  ADW            PCBCACHE         Save Shopping Cart (pcbcache) is crashing component browser
867842  CAPTURE        PROJECT_MANAGER  Capture crash with 'Open File Location"
868306  CAPTURE        CONNECTIVITY     mirror vertically removes junction creates extra nets
3 ~9 O' t8 m( w' t' b  b, h# O882677  EMI            RULE_CHECK       bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
891439  ALLEGRO_EDITOR INTERACTIV       moving cline segments
) l/ b$ q& P9 _# A  y8 @- i- n' U  [893544  ALLEGRO_EDITOR INTERFACES       IPC-D-356A netlist issue with BB vias.
+ M/ e7 ]) R8 v9 ~0 F893765  ALLEGRO_EDITOR PARTITION        Mail command not sending out email on Linux platforms.
894390  SIP_LAYOUT     EXPORT_DATA      Generate all balls in the xml file for export to EDI's readPackage command
4 a" W0 a; h( [3 o& P6 |895933  APD            DATABASE         Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
+ I, B5 w; @6 x896598  ALLEGRO_EDITOR PLACEMENT        error message is misleading
& c, }" B, F: D897196  CIS            LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library
898598  ALLEGRO_EDITOR MENTOR           Negative planes from Mentor Board Station not being translated.
899556  ALLEGRO_EDITOR ARTWORK          Import artwork seems not to work correctly.
# P2 u2 M, B  ~5 B900501  ALLEGRO_EDITOR PLACEMENT        "Place Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5
901141  CIS            EXPLORER         Japanese character appear garbled in CIS explorer window.
901666  CAPTURE        OTHER            Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
902066  ALLEGRO_EDITOR DRC_CONSTR       Shape in Region not follow the constrains
902349  CAPTURE        LIBRARY          Capture crashes while closing library
902508  F2B            PACKAGERXL       SPB16.5 Packager-XL consumes much more memory than 16.3
902841  CAPTURE        GENERAL          Capture Start page does not show
; O" o* x! {5 k8 ~2 m( D902876  F2B            PACKAGERXL       Packager fails on the design upreved in 16.5
902959  CONCEPT_HDL    HDLDIRECT        HDLDirect Error while saving design
! _0 D6 s; N. T903171  PSPICE         NETLISTER        Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?
903713  ALLEGRO_EDITOR PARTITION        Placement Replication do not work fine in the Design Partition
6 q5 X/ u% Z( K% K8 K8 g* r3 Z903799  SIP_LAYOUT     DIE_EDITOR       Disappear die pins after exiting co-design die editor
: c  A# T7 ^& F( K904021  ALLEGRO_EDITOR OTHER            Export PDF from SPB 16.5 produces a file not text searchable
904339  CONCEPT_HDL    CORE             new design crashes using the attached CDS_SITE
1 o' Q4 [1 h* ^) h904522  F2B            PACKAGERXL       Part will not package in 16.5  but packages in 16.3
  I& j, |% x1 }904764  APD            OTHER            Enhance Scale Factor of Stream Out to support 4 decimal places
3 c# ^: e) o0 ~) U2 X! t2 g0 n904771  ALLEGRO_EDITOR MANUFACT         Pin Number display issue.
* a# X! }0 M5 _( d' m+ `8 r904853  ALLEGRO_EDITOR GRAPHICS         Enhancement for showing Static shape as it was seen in 16.3
905144  CONSTRAINT_MGR ECS_APPLY        Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
905314  F2B            PACKAGERXL       Import physical causes csb corruption
5 M8 q* A4 z) c4 f- y! f- J" l905337  CONCEPT_HDL    CORE             ConceptHDL crashes after Import Design process.
905533  ALLEGRO_EDITOR INTERACTIV       Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
905796  CONCEPT_HDL    CONSTRAINT_MGR   Fujitsu CM issue inaccurate concept2cm diff pair issues
905811  CAPTURE        EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid
906118  CONCEPT_HDL    CONSTRAINT_MGR   Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
906153  ALLEGRO_EDITOR SCRIPTS          Unable to run allegro script in batch mode on the attached board.
& |! m7 I7 g1 B( d: E& c2 x. q" z906182  APD            EXPORT_DATA      Modify Board Level Component Output format
' Q* t6 `' y+ c' L0 W$ E0 r906200  ALLEGRO_EDITOR DFA              Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element
- L$ \) N- }& U. Y, P906517  PSPICE         PROBE            PSpice new cursor window shows incorrect result.
906627  ADW            COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
906647  SIG_INTEGRITY  LIBRARY          lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run
906673  F2B            PACKAGERXL       Ignore the signal model validity check during packaging
* Q4 e& I( L5 G; Y, E& b906688  ADW            LRM              A copy of source design gets created in worklib of target design after 'Import Design'
906750  ALLEGRO_EDITOR PARTITION        Importing design partition removes the testpoint reference designation
906874  PSPICE         NETLISTER        Error less than 2 connections for unconnected hierarchical pin
907095  F2B            OTHER            Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
907424  ALLEGRO_EDITOR GRAPHICS         Allegro add option for pre 16.5 shape display
( _8 i1 A* f- d+ F* {907490  CAPTURE        NETLIST_LAYOUT   16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.
( W6 k) l& c/ L( }& B9 `. M907884  SIP_LAYOUT     MANUFACTURING    Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
907885  SIG_INTEGRITY  OTHER            Matchgroup targets lost when importing netlist  to Allegro layout in HF31
907929  CAPTURE        TCL_SAMPLE       TCL command to delete a property from parts in a library is not working correctly
907933  SIG_INTEGRITY  OTHER            Single line impedence not working in OrCad PCB Professional
# j; b, B- u  A& u4 q907963  CONCEPT_HDL    CORE             Design uprev issue when moving from 16.2 to 16.5
9 G8 t' P3 f& s0 w908000  SIG_INTEGRITY  OTHER            Inconsistence z-axis delay reported on Tpoint when define at via location.
908057  CONCEPT_HDL    CORE             DE HDL crash with the cut and paste of a signal name
908060  CONCEPT_HDL    CORE             CTRL+LMB Option not working correctly in 16.3
908210  CAPTURE        CONNECTIVITY     Connection is being lost while dragging a component
908241  CAPTURE        DRC              DRC error column is blank in DRC markers window in 16.5
& N6 X. p" \2 ]1 n908339  RF_PCB         BE_IFF_IMPORT    mechanical holes VIAFC are not at the right place
. y- r! j6 f& S! |. t908534  SIP_LAYOUT     SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays
+ k% w  ?6 T" S/ m908535  F2B            DESIGNVARI       When I try to view my variant file the variant editor crashes
908595  APD            3D_VIEWER        Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
908849  CAPTURE        ANNOTATE         Getting crash while annotating the attached design
, h7 Q9 b' z) a) g, N5 U2 `908874  CONCEPT_HDL    CORE             Part Manager - No Part Found error when using CCR# 775788 feature
909077  CONCEPT_HDL    CORE             After packaging pin numbers remains invisible even when $PN
5 F7 z4 Q: w6 x/ P6 O8 p( h909104  ALLEGRO_EDITOR SYMBOL           Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.
909417  ALLEGRO_EDITOR REPORTS          "report -v upc" returns 'Segmentation fault' on Linux
! i# e- k3 W5 N/ P& q909635  SIP_LAYOUT     DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
, d5 m8 U- w* t& D# Q" T6 e& o& f909749  ALLEGRO_EDITOR MANUFACT         Allegro Crash during dimensioning
909760  SIP_LAYOUT     MANUFACTURING    Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
909861  F2B            PACKAGERXL       NetAssembler broken within the latest 16.30.031
0 {  z; z; M1 x0 C; T! u1 k( b- o4 u3 p910006  CONCEPT_HDL    INFRA            Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
/ f2 }) X% ^( `0 q910141  CAPTURE        NETGROUPS        Modify NetGroup definition does not update Offpage Connector
) r  C, G$ u8 H( l. K' J2 s1 I910340  ADW            LRM              Import design in schematic, only 1 page import,  the entire block is getting imported.
7 }8 |4 D% ]# g) H% e% P910678  SIG_INTEGRITY  OTHER            The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
/ z. R( F$ ^( o0 z8 \0 L4 N$ _910713  F2B            DESIGNVARI       Variant Editor crashes when you click web link under ?hysical Part Filter?window.
910936  F2B            PACKAGERXL       ConceptHDL subdesign net name is inconsistent
; t, y! ]. U9 y911530  ALLEGRO_EDITOR SYMBOL           Package Symbol Wizard does not create symbol with the name given
911631  CONCEPT_HDL    CORE             DEHDL crashes when opening a design
% I" T, ^/ `" ~; ?0 S0 D+ r912001  ALLEGRO_EDITOR OTHER            option_licenses entries are made in allegro.ini even when not set as default
1 h) P% j; |# \( y. ]: h912459  F2B            BOM              BOMHDL crashes before getting to a menu
( a' U2 R$ g5 `9 }# J913359  APD            MANUFACTURING    Package Report shows incorrect data
9 K5 m3 M+ D0 x! U0 f/ @下载完了，安装中

cxyjoe

楼上的大侠共享一下啊

text108

foxconnwj大侠共享一下啊

每天学一点

好快呀

fangqwas

快...

suiwinder

foxconnwj 发表于 2011-7-28 08:18
5 B: i! f; h5 Q) V* ~' w, aDATE: 07-24-2011   HOTFIX VERSION: 002
============================================================ ...

如果可以共享就和大家分享下，如果不能就不要说风凉话！
# {2 _. n% M* W1 [+ N, r9 S

hzqydq

希望大家共享一下