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标题: Orcad capture生成网表时出错，大家帮我看看 [打印本页]
作者: lyf9908    时间: 2011-6-12 12:00
标题: Orcad capture生成网表时出错，大家帮我看看
大家好，以前用AD6,PADS, 与在用SPB16.2,很不习惯呀。
# ^) [$ f9 \" v8 Y' `. F+ O( j' y     在做完原理图，DRC检查没有错误后，生成网表时，出现：
% C2 Y4 n: ^: h   #248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'.  Each section must have at least one non-common pin.
: }5 B9 I* |' J+ T" C        Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.- W! Z2 G# U2 }7 [+ [
      我检查了原理图SYMBOL和PCB封装，也换另外的PCB封装试了试，错误依旧。5 U6 G$ ^2 M" v: T
  大家帮我看看，是什么原因呀。) W) X9 |+ ~6 R+ T5 _
    我在画原理图时还碰到其它的问题：
5 b: z- f  ~6 R3 _& I      1：元件编号如电阻电容之后，总自动出现一个A或是B,  如：R120A
+ e" I" S6 t2 F( `9 o$ ^, m% z) k      2: 在COPY一个元件到另外一个地方去时，本应每COPY一次编号都自动增加，可现在是每COPY两次，编号才自动增加一次。& i# Q- J) d+ m  K& v$ A2 _
     原理图工程我加在附件里了，大家可以打开F3文件帮我看看。
3 I; G+ Q( D* @9 w; i5 J! E  d     为方便大家检查，我把生成网有的出错贴在下面了：
: h$ g; s& f4 y* Z& B      ********************************************************************************: L# W) S* e+ Q' p7 p  x
Design Name:. [' ^9 x0 D5 n+ m7 P9 S! o6 I7 ~  {' W
E:\Hi3515FJ_CADENCE\hi3515fj.dsn$ _, e; O3 j; J5 V) L- b
Netlist Directory:* I' ?/ }/ _3 {: v, _" ]
E:\HI3515FJ_CADENCE\NETLIST
/ @; w& G6 `, @6 G; ~) HConfiguration File:7 n8 h5 H  u, S8 a
D:\Candence\SPB16.2\tools\capture\allegro.cfg
5 k4 O. o9 n% x6 U- GSpawning... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"3 f  F1 \, a) D) a7 m3 o8 {: ?- U
#1 Warning [ALG0016] Part Name "PHONE JACK-4_0_PHONEJACT_4_PHONE JACK-4" is renamed to "PHONE JACK-4_0_PHONEJACT_4_PHON".5 }7 P3 {& L9 K; Q
#2 Warning [ALG0016] Part Name "SN74CBT16214_0_SOP56-20-250-550_SN74CBT16214C" is renamed to "SN74CBT16214_0_SOP56-20-250-550".
4 U, F* N2 i# E4 I! @Scanning netlist files ...& B+ u8 C/ p) V
Loading... E:\HI3515FJ_CADENCE\NETLIST/pstchip.dat- l* ~. Y+ g" O* D2 }% f% z  H
#248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'.  Each section must have at least one non-common pin.* }7 m1 B5 f, Y4 H
        Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.
, j+ D: y, r$ x+ D  F              ERROR(SPCODD-47): File E:/HI3515FJ_CADENCE/NETLIST/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again.
! V8 ?( P0 g, P" Z#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schema3 B0 t; @% v( a% L
tic and rerun packaging.
% z+ v' |  e$ y  i/ ^, I" ^' i#3 Error   [ALG0036] Unable to read logical netlist data.
7 Q, X% H5 H% z. w# EExiting... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint") B$ }2 G& v7 T0 @5 q. L

' D; \+ B1 d* ?- [9 t*** Done ***




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