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标题: PCB Designer’s si guide [打印本页]
作者: snowwolfe 时间: 2008-5-26 11:07
标题: PCB Designer’s si guide
PCB Designer's SI GUIDETable of Content ! k; F- [! i" ^6 T
Basics of SI___________________________________________________________________5 ! L' B4 Q3 S2 U, C/ ? ?/ e
1.1 When Speed is important? _____________________________________________5 # _2 P; F U7 a4 m
1.1.1 Acceptable Voltage and timing values ________________________________5
/ |& {* \' q& z* C9 [) j F% P- b1.2 Signal Integrity ______________________________________________________5
6 s1 l2 J2 {! V1.2.1 Waveform Voltage Accuracy _______________________________________5
; P6 ?% A8 M5 O9 |: c, \1.2.2 Timing_________________________________________________________5
- c* [# D. e7 @1 z) ~6 Q1 {* H1.3 Speed of currently used logic families ____________________________________5
8 p6 [% ^3 Q* V; N1 F% G1.3.1 Transition Electrical Length (TEL) __________________________________6 * K6 ~2 h7 v" |4 k+ X1 s' \2 e0 ^
1.3.2 Critical length ___________________________________________________6
, I1 B8 u' N1 P( [4 S1.3.3 What is Transmission Line? ________________________________________6
8 V) `+ |6 S, u1.3.4 What is moving in a Transmission line?_______________________________6 8 ~ q, P3 z; [+ ]3 U* P/ \
1.3.5 Power Plane Definition____________________________________________6
( @: f& l$ L1 H- A1.3.6 The concept of Ground ____________________________________________7 " ?" Y, O: Q, w
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
) Z) G. G% R' c; K# V; C/ J# v+ `1.5 RLC Transmission Line Model _________________________________________8
/ s; N8 u( p3 r6 w, {7 _# R. C1.5.1 What is Impedance? ______________________________________________8
" O; Q: _7 B2 M. ~1 G2 {* P1.5.2 A Practical impedance equation for microstrip _________________________8 " C6 e8 c& h1 T% c0 z0 T9 l
1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10
/ `) R6 N; K4 t$ S2 o2.1.1 Summary______________________________________________________10 ! w; O% A1 O2 e+ c1 @8 P5 a- x
2.2 Examples of dynamic interfacing problems _______________________________10
: S* A2 C5 W* T5 P( u3 ?2.3 IC Technology and Signal Integrity _____________________________________12 9 a8 z+ p( H- c, G# `7 Q. O
2.4 Speed and distance __________________________________________________14
: |( {3 @! u7 i2.5 Digital signals: Static interfacing _______________________________________15
. r6 t# A) Y; }1 ?/ ?2.6 Digital signals: Dynamic interfacing ____________________________________16
. c1 r8 @" @2 F, C6 q; k2.7 Review questions ___________________________________________________18
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3 Interconnection Models____________________________________________________20
" |! D- T8 O8 _- o2 J3.1 Summary__________________________________________________________20 0 T, _, R, e" w) g# s3 S/ o2 n
3.2 Reference model for interconnection analysis _____________________________20
9 U& h- ?! }. Q$ M; y! S8 _7 [* X3.3 Receiver model_____________________________________________________21
) h" }* ~; _1 E) D3.4 RC interconnection model ____________________________________________23 ) A" K! c5 | [3 c% g
3.5 Parameters of the interconnection ______________________________________25 ' k# l. k# d0 B$ `# x
3.6 Refined models _____________________________________________________26 7 d+ T9 Z$ X4 c. i8 O: x; i
3.7 Review question ____________________________________________________28
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4 Transmission Line Models _________________________________________________31
' z5 S E5 r7 C) m% Q& V4.1 Summary__________________________________________________________31 ; `: y% _4 I+ O) G# m1 Q
4.2 Transmission line models _____________________________________________31 $ Y9 Q) j$ S( C- v
4.3 Loss-less transmission lines ___________________________________________32
7 b# X( e# O7 R- ]4 `4.4 Critical Length _____________________________________________________34
2 e6 } i$ d) w# r. q4.5 Reference transmission line model______________________________________35
& [6 t+ @# P2 {6 h. `$ R/ V( U4.6 Line driving _______________________________________________________36 6 W; G/ m* x6 z0 q' F9 {$ R% k
4.7 Propagation and reflected waves _______________________________________37 2 R7 m2 \' D/ R" Y1 L$ B
4.8 A sample system____________________________________________________39
0 q% [5 |* j. R# M+ E4.9 Review questions ___________________________________________________42
5 T- n$ \; ^5 W/ I# gPCB Designer’s SI Guide Page 2 Venkata
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3 {2 R* N+ M. j( | z( r5 Analysis techniques _______________________________________________________45
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5.1 Summary__________________________________________________________45
& h- r( Q1 r6 z! _7 q3 @5.2 Transmission time and skew___________________________________________45
K+ y& \8 j/ K2 L- f' p3 Q5.3 Effects of termination resistance _______________________________________46 3 D! I% L6 X! s! k
5.4 Lattice diagram _____________________________________________________48 , m* h4 i2 m4 S; ~
5.5 Examples of Real Lines ______________________________________________49
. g/ P3 r- `! s8 L/ W5.6 Simulation code ____________________________________________________51 " P4 k: g( r8 E) P1 a9 J/ H, S/ C
5.7 Examples of results__________________________________________________54
9 R3 P( U# F9 E( M: w: Y$ t6 [5.8 Review questions ___________________________________________________55 7 l+ `/ A Q" p6 \5 r" u
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6 Design guide for interconnection ____________________________________________57
. b( A/ k0 |5 \# J6.1 Summary__________________________________________________________57
- ~9 N9 \2 B- X7 V6.2 Incident wave switching ______________________________________________57
~" }! r/ Z6 ]2 r- T$ |6.3 Effects of capacitive loading __________________________________________58
( c# m0 `" ?$ a! q9 c; \+ Y6.4 Termination circuits _________________________________________________59 % \3 R" @# Z- h/ S- k% u" x. {
6.4.1 Passive termination______________________________________________60
- y$ A+ B% [3 V6.4.2 Low power termination___________________________________________61 3 m I4 R$ @% f
6.4.3 Active low power termination circuit. _______________________________61 ) Q6 u8 c' Y# |- `2 ~: t' t
6.5 Driving point-to-point lines ___________________________________________62 0 S9 _7 {; \; f2 H$ |: @
6.6 Driving bused lines __________________________________________________64 : K; h/ ^; E2 X' F1 O9 ^5 j
6.7 Design guidelines ___________________________________________________67 " Q N5 C" Y/ m, E# x; j% D
6.8 Review questions ___________________________________________________67
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PCB Designer’s si guide.part1.rar
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PCB Designer’s si guide.part2.rar
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作者: snowwolfe 时间: 2008-5-26 11:09
Signal Integrity in Digital Circuits ___________________________________________70
. m) u# a* d) W# m. o0 \* ~6 o7.1 Crosstalk __________________________________________________________70 2 B* I, e; A8 {
7.1.1 Summary______________________________________________________70 C; a+ J; Y8 u) v5 S
7.2 Examples of signal integrity problems ___________________________________70 ' e0 C3 D$ A: V# _" M# F
7.3 Simplified Model for Crosstalk Analysis _________________________________71
. F* j* u! q" i9 w' g7.4 Forward and backward crosstalk _______________________________________74 + M: L, W1 ^+ G( n& `
7.5 Examples__________________________________________________________76 - _1 L* }2 c3 D: {0 [, u
7.6 Near-end and Far-end crosstalk ________________________________________80
) v$ F( n; ^7 j" x$ b: S7.7 Review questions ___________________________________________________81
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8 Design Guide to Handle Crosstalk ___________________________________________85
! t7 `' Z8 b1 a" h8.1 Summary__________________________________________________________85
, G+ V6 P2 v8 o; Z7 s, g8.2 Effects of Crosstalk __________________________________________________85
9 P! n3 w/ N$ B8.3 Passive countermeasures _____________________________________________86
+ C3 a1 |/ G, W0 W+ J2 _' P8.4 Active Control of Crosstalk ___________________________________________92 - G$ b3 k+ @$ t2 K) Y/ J3 w' K
8.5 Review questions ___________________________________________________94 6 [4 r0 }, U$ l5 b0 s! O9 Q
9 Ground Bounce and Switching Noise_________________________________________97
# I* ]- |; @ S( p9.1 Summary__________________________________________________________97
, T4 j7 R0 i9 j9.2 The totem pole Current Spike__________________________________________97 / \0 D( n9 F5 f" s: v+ h5 S
9.3 Current flow in the output capacitance __________________________________100
- h' U" U( e& P3 a' w% R2 A9.4 Total Ground Bounce _______________________________________________100
0 b5 p; ~- {. Z, |7 G* v/ N7 F- @9.5 Review questions __________________________________________________105
o) B a7 r; h& D0 v$ b2 U10 Design Guide for Ground & Power Distribution _____________________________107
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10.1 Summary_________________________________________________________107 5 p4 o/ r6 ~( g2 a" w3 R7 N
PCB Designer’s SI Guide Page 3 Venkata
& x$ G6 m6 i2 K* ]7 J5 ^10.2 Decoupling Capacitors ______________________________________________107
I3 G6 Z" {+ ?. ]. \ `% p+ C10.3 Placement of bypass Capacitors _______________________________________113 " `8 O( i$ ]' {: @6 p; F
10.4 Ground and power distribution________________________________________114
: P8 N2 j: a/ M9 P- p10.5 Clock distribution __________________________________________________115 " t' m( g- }) y! u1 }/ x) P
10.6 Review Questions __________________________________________________118
. }) m6 M$ I1 B; U. H! Q! ?! O11 Laboratory Experience _________________________________________________120
. I* C. f- S! @- ~/ J11.1 Summary_________________________________________________________120 ) J# H' Q( O- Y R
11.2 Aim of the experience_______________________________________________120 6 q. }# c2 f1 n& G$ c
11.3 Generator Parameters _______________________________________________122 / _% V- P# A0 u
11.4 Cable Parameters __________________________________________________123
q) e* z6 ]" {. r# u11.5 Mismatch at driver and at termination __________________________________124 ! m+ {: e3 h, }' {
11.6 Capacitive Load ___________________________________________________125
; M! M8 ?) p6 h- y' [11.7 7. Time-domain reflectometer ________________________________________127
* C+ L; [! K+ \& Y& z11.8 Driving the line with logic devices _____________________________________128 & ~$ c1 F: T) M6 Z7 ^( Z7 Q5 ~( V. M( w
12 SI Analysis Strategy____________________________________________________133 1 H6 O+ ?. h. ]* |9 D: J" C7 P
12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133 ; m9 J' V0 _- L) R
12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
" p- J" r4 P" y& ?1 G; X12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
' `, t; _! |4 V5 t5 U; S! |12.3 SOLUTION SPACE ANALYSIS _____________________________________135
7 U" A; ^+ E! A8 H; R, F7 a1 {12.3.1) @3 x. K; V: E: y$ e l% y
STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
& _+ u8 X9 g# [" Q( d/ V12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
' a. e1 v* a' Y# F/ ~) }1 t$ F2 A. J12.3.3: W; T' C$ n3 ]8 i
STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136 2 O$ g' g" P4 k) o; z. X& t
12.3.4
& X9 C7 Z7 |0 A7 E5 r- v6 vSTEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136 ( s7 R. W4 E9 ~& l- h
12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
# M; D+ m2 ?5 h4 Y& @12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137 % t+ T1 @5 ^& c" H
12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
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STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137 5 n# }3 e$ ?' V1 E! G6 [
12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138 $ Y# h U# A3 A! s/ `) A4 A
12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
% E, A% `( \& j8 |3 N; D3 C) x) ~12.4 CONCLUSION____________________________________________________139
; P* Y' `5 j- A/ Z z13 Glossary _____________________________________________________________141
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作者: sshunhua1981 时间: 2008-5-26 16:33
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作者: andy.wei 时间: 2011-7-8 11:30
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