PCB Designer’s si guide

snowwolfe

PCB Designer's SI GUIDETable of Content
9 t: w1 H5 c' G& r( k, T1 z& r4 qBasics of SI___________________________________________________________________5
1.1 When Speed is important? _____________________________________________5
1.1.1 Acceptable Voltage and timing values ________________________________5
1.2 Signal Integrity ______________________________________________________5
  W9 f$ T2 I% W6 p& P" Y5 u1.2.1 Waveform Voltage Accuracy _______________________________________5
1.2.2 Timing_________________________________________________________5
. o4 w' s: V# h3 _, X1.3 Speed of currently used logic families ____________________________________5
/ b# _; p( i/ d0 q' p9 J1.3.1 Transition Electrical Length (TEL) __________________________________6
1.3.2 Critical length ___________________________________________________6
1.3.3 What is Transmission Line? ________________________________________6
8 I: t/ u2 j5 k/ x9 Z6 Q, ^  k; S. }1.3.4 What is moving in a Transmission line?_______________________________6
1.3.5 Power Plane Definition____________________________________________6
1.3.6 The concept of Ground ____________________________________________7
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
3 c: ]8 k- y/ l1 h, J0 j4 G1.5 RLC Transmission Line Model _________________________________________8
/ g8 }& c4 U& a" p# D: A1.5.1 What is Impedance? ______________________________________________8
2 Z8 d4 D0 \! D4 [% H& y1.5.2 A Practical impedance equation for microstrip _________________________8
1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10

# ]* I9 c/ U) y+ V+ Z7 T# b# J& d2 T2.1.1 Summary______________________________________________________10
2.2 Examples of dynamic interfacing problems _______________________________10
% ?8 E1 \/ Y1 s3 I2.3 IC Technology and Signal Integrity _____________________________________12
2.4 Speed and distance __________________________________________________14
% S6 M% E* D$ S- U2.5 Digital signals: Static interfacing _______________________________________15
- [% i2 e4 t1 B2.6 Digital signals: Dynamic interfacing ____________________________________16
$ ]9 f3 A; E9 {9 F" x3 H9 B2.7 Review questions ___________________________________________________18


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3 Interconnection Models____________________________________________________20

; @3 R5 c- n2 p0 |# j$ S3.1 Summary__________________________________________________________20
5 R8 A: T7 b. O: `+ N3.2 Reference model for interconnection analysis _____________________________20
! ^1 J9 X. K! w8 |# b- z3.3 Receiver model_____________________________________________________21
: {! |* `" }3 c8 v0 g3.4 RC interconnection model ____________________________________________23
$ u& V2 g/ @7 w( w' u" T; y3.5 Parameters of the interconnection ______________________________________25
3 f- }2 r. R1 ?3.6 Refined models _____________________________________________________26
3.7 Review question ____________________________________________________28
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4 Transmission Line Models _________________________________________________31

% C$ R) z4 }# y% \4.1 Summary__________________________________________________________31
4.2 Transmission line models _____________________________________________31
4.3 Loss-less transmission lines ___________________________________________32
3 G8 K: U7 t: T7 j& W( L4.4 Critical Length _____________________________________________________34
2 p6 X, Q0 c) e- b4.5 Reference transmission line model______________________________________35
" I" |2 U, ~! N) d/ L4.6 Line driving _______________________________________________________36
% `8 F, U5 k# ~4.7 Propagation and reflected waves _______________________________________37
4.8 A sample system____________________________________________________39
4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45

5.1 Summary__________________________________________________________45
7 e- X& Q1 G/ s5.2 Transmission time and skew___________________________________________45
5.3 Effects of termination resistance _______________________________________46
5.4 Lattice diagram _____________________________________________________48
% g- V1 Y; e, O2 G  D4 E$ h" m2 ?5.5 Examples of Real Lines ______________________________________________49
5.6 Simulation code ____________________________________________________51
& R& f% N  u# ?( e2 X  ^! n7 \5.7 Examples of results__________________________________________________54
) Y6 f, y2 t  E( k! R. `5.8 Review questions ___________________________________________________55



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6 Design guide for interconnection ____________________________________________57

6.1 Summary__________________________________________________________57
6.2 Incident wave switching ______________________________________________57
6.3 Effects of capacitive loading __________________________________________58
6.4 Termination circuits _________________________________________________59
6.4.1 Passive termination______________________________________________60
6.4.2 Low power termination___________________________________________61
8 Y2 `% S) x+ t: r6 |& q, r6.4.3 Active low power termination circuit. _______________________________61
9 N) T. `- M" P; d" _" ]" t6.5 Driving point-to-point lines ___________________________________________62
6.6 Driving bused lines __________________________________________________64
7 u3 `9 X  @% k! d! E( _2 F& |$ {! d6.7 Design guidelines ___________________________________________________67
0 w9 S: _( x- W2 Z, {% E6.8 Review questions ___________________________________________________67

snowwolfe

Signal Integrity in Digital Circuits ___________________________________________70
% t6 |8 k- [* }8 g1 b% o7.1 Crosstalk __________________________________________________________70
! J0 u' J( h5 @7.1.1 Summary______________________________________________________70
3 z* g/ w5 y5 g7.2 Examples of signal integrity problems ___________________________________70
1 M5 K& N. y5 }3 ~% B' o/ _$ a7.3 Simplified Model for Crosstalk Analysis _________________________________71
/ M$ K- R% V1 S: i7.4 Forward and backward crosstalk _______________________________________74
7.5 Examples__________________________________________________________76
5 k; S( J  }2 z2 Y" K% f9 C7.6 Near-end and Far-end crosstalk ________________________________________80
7.7 Review questions ___________________________________________________81


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8 Design Guide to Handle Crosstalk ___________________________________________85

8.1 Summary__________________________________________________________85
8.2 Effects of Crosstalk __________________________________________________85
8.3 Passive countermeasures _____________________________________________86
8.4 Active Control of Crosstalk ___________________________________________92
0 O" e6 S3 A5 S" K! k8.5 Review questions ___________________________________________________94
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9 Ground Bounce and Switching Noise_________________________________________97

9 k, P4 Y+ n! U- `9.1 Summary__________________________________________________________97
# w! t! X. d' o- X9.2 The totem pole Current Spike__________________________________________97
9.3 Current flow in the output capacitance __________________________________100
) o) L$ u: V* n% I! d! w6 x9.4 Total Ground Bounce _______________________________________________100
9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107

9 D  e4 |, Y# s6 g" r10.1 Summary_________________________________________________________107
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PCB Designer’s SI Guide Page 3 Venkata

10.2 Decoupling Capacitors ______________________________________________107
; n* b7 T4 t9 m10.3 Placement of bypass Capacitors _______________________________________113
10.4 Ground and power distribution________________________________________114
10.5 Clock distribution __________________________________________________115
10.6 Review Questions __________________________________________________118
8 R: H1 a) B: S+ o* I" F6 ?+ g11 Laboratory Experience _________________________________________________120
11.1 Summary_________________________________________________________120
% Y( g# P' T4 r. A# C7 ]11.2 Aim of the experience_______________________________________________120
, T$ T$ J7 }+ Q. x6 [% y11.3 Generator Parameters _______________________________________________122
' a7 P4 ^" `1 }% A11.4 Cable Parameters __________________________________________________123
11.5 Mismatch at driver and at termination __________________________________124
. E  O" B; f* t11.6 Capacitive Load ___________________________________________________125
0 ~* M/ v. I5 }2 f11.7 7. Time-domain reflectometer ________________________________________127
11.8 Driving the line with logic devices _____________________________________128
12 SI Analysis Strategy____________________________________________________133
) V, i6 i. H% @2 e+ s0 g12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
! O% a" |- y" K12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
' V9 U8 k( m* S7 f12.3 SOLUTION SPACE ANALYSIS _____________________________________135
12.3.1
STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
, Y' I8 u6 U, Z# z2 U+ e: L4 h12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
12.3.3
% V3 X% n6 e0 j3 v; QSTEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
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STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
- Z' r+ q7 A  x9 P12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
% W0 [; B& e" j" b% r12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
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9 v! f( Q$ J8 ]! N1 Y3 cSTEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
: K; |# Q# p2 L! F2 S9 Y0 X" f9 d12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
12.4 CONCLUSION____________________________________________________139
13 Glossary _____________________________________________________________141

PCB Designer’s SI Guide Page 4Venkata

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