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标题: CADENCE SPB RELEASE 16.3 README -- UNIX Version 已经RELEASE,期待windows 版本 [打印本页]
作者: whq888    时间: 2009-12-9 13:24
标题: CADENCE SPB RELEASE 16.3 README -- UNIX Version 已经RELEASE,期待windows 版本
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7 k& Q- `! M$ k: d# _
, \/ F+ h) z- \  `( HCADENCE SPB RELEASE 16.3 README -- UNIX Version% I% i# I) b& h

- T$ f( A, t& k===============================================
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0 U3 t% @9 `$ X) F6 wINSTALLATION GUIDE
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2 R4 F7 Q# p% n2 Z8 X--------------------0 g9 h% o! ]  f, [( ^
You can find the UNIX installation guide on Cadence Online Support or the5 |- t8 m1 ~" U4 s5 m8 B2 [
Cadence downloads site.
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/ x3 r# S4 H4 w6 w' uMIGRATION INFORMATION
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-----------------------
0 c$ {' ^6 G9 q, h+ WImportant migration information is contained in the "Migration
& ^8 u( B: @8 k  o" n. f5 x6 bGuide for Allegro Platform Products Release 16.3", which is
* G0 P9 }" v) p- `3 k, T( E, {) D7 J8 Davailable when you install this software or on Cadence Online Support.
9 ^9 V+ k, a% C3 M( R. C% ]3 @2 c, m. ~6 s( j1 M5 K; @' d$ x9 T# z

  |+ [- I; {: w# GSYSTEM REQUIREMENTS
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0 w1 x& ]% D& d8 U, M* }----------------------8 M) {' z/ N. D$ v

( P& \9 Q* w. A% V6 f9 @Information about minimum and recommended system requirements can be
6 ?  c# t7 p2 Z3 y3 pfound in the "Allegro Platform System Requirements" document in the
5 |7 w7 A, k. M. iCadence product documentation or on Cadence Online Support.
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+ Y2 O; W* Z. G" R# X- Z/ x; O! S4 ~$ ]0 ~( w  z) B
WHAT'S NEW
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Product release notes are available at:& S8 m  V( @% R# p+ F6 O: p8 y
[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer[/url];
6 r* ~+ v2 E$ V' D3 x& x0 J- Gsrc=pubs;q=landing/spb163/prodList.html
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8 c# T4 }8 m0 t! Z" y- B" Y
4 a' k8 e9 y& b( F$ L/ PKPNS( h# `7 C  ]* d5 a; S5 H; U, I
----! c$ o, f5 U$ l( ]/ F
The Known Problems and Solutions (KPNS) document is located at:
" k& B1 j  o0 k- y3 k( P- O[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer[/url];
, L! Y9 s9 J/ Z4 tsrc=pubs;q=landing/spb163/kpnsList.html: ~" w7 Q1 }5 y8 r6 }8 t: v% |
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# l  `! P7 m  y7 LAllegro /SigXplorer ABIML LIBRARIES FOR DEFAULT TRACE MODELS/ D: G, t: @0 ]: U

$ B1 j" w/ o! S+ D9 U) e--------------------------------------------------------------5 \- g" _' m8 `' D) Q
The Allegro /SigXplorer ABIML Library is a free library that includes ABIML
) f" [: |0 D* Glibraries for SigXplorer default trace models with surface roughness effect.
# A0 h+ s8 D; ]( n- \- UIt is designed to provide accurate trace models in Allegro /SigXplorer without
; h- u7 i$ {+ P1 V/ V( `  Ktime consuming EMS2D solver runs. The libraries can be found at:
, j% b7 {& t9 x0 D6 N: mhttp://www.cadence.com/products/pcb/pages/Downloads.aspx9 @1 N1 I. B1 A, j$ E, D/ [

5 |- r. [) t  J' J4 u4 gThis ABIML library is provided free of charge for use with Allegro and SigXplorer. 2 S6 E- i, A3 g  O
The library is provided as a zipped archive, with installation instructions included.
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CUSTOM ENVIRONMENTS; d% l+ }. Q4 z/ F1 N- v

. S" m/ b0 _; q3 U+ M-------------------
/ _# e5 F4 k6 X1 T+ k! `Customers using custom batch files or scripts to set up their environments must add 2 w" u/ k8 o' {4 U4 f
the following to their path. There is the potential that some Allegro products may not  a! u4 V) v) o9 m' ]! E
launch without this setting.
* F, L. r& m- T4 j$ d%CDSROOT%\OpenAccess\bin\win32\opt1 p- ~2 o! T$ p; f

" F/ F$ w' f0 J3 B5 M! H, \8 r1 h. X2 [; F% K
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7 G8 R, k7 k8 q) f# _. {/ x5 x. a. nList of Fixed CCRs8 J5 P5 B' ~, P' u8 L0 B$ _
-------------------
& g# k8 l# H; E- Y0 T+ E-------------------
9 |, X' t: O! u% F& ~+ l; c5 h* e! Y. ?% |/ U
) k  c3 W* y" f. T+ u4 P
ENHANCEMENT CCRs3 [* }8 [. U7 s
----------------
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CCR Description9 a4 K9 Z; _: J  t5 P! p! O, M
----- -----------
" E6 Q/ V; ?, ]( C/ Y----- ----------- 2 K* ^' n! ?% n
& R& a  P( w# b% ]
7419 Customer menu options added to Allegro menus
0 d+ P& a: z3 q7 \3 I. H8230 Use via in area constraint does not work
. z( O0 [! S* b: V6 W10658 Modify default formatting for Label texts and linewidths/ u& ^% v9 z+ I7 e
12216 Cannot set color or line width for wires on net-by net basis. u9 j+ r1 H- k  `
13083 flip/mirror design to back side. q" \1 O0 w8 B+ h7 h; ]6 d- h) i6 k
13373 Select length of pin graphics3 i6 z: A- {# W( Z9 k
18072 Add docking option for probe cursor box.$ Q4 n0 R7 I8 ^+ ]( ^8 [6 S
21451 Change Probe print trace color yellow to alternate.
9 w: Y$ L6 j- B9 c0 [1 e5 _* E  x* V32798 pxllite complex hierarchy netname enhancement
; r! `3 D% H! G- l- e: ?3 T: l39600 Option to see time spent on allegro database/ A0 Z7 f5 l) W; h8 v$ u
60427 Add different subclasses for pin_number top and bottom2 J! V) i+ n7 k) t3 E% B
132769 Footprint viewer in CIS should also show pad spacing info6 D% F: x3 H3 l! H! \+ S+ k
158838 Need easy way to delete marker
0 _  ?0 h" `7 G) }159977 need attribute mapping capability in mbs2lib and mbs2brd) f7 a: k: n: @
164790 Improve autorouting quality on diff pair w/match length rule
  o; v4 w* C/ ^205909 Constraint Manager displays in Allegro no graphic mode
3 i* I1 j! U( {9 B210027 Delete dynamic shape removes net name from copied vias
/ |  J$ q+ [4 d0 A222127 PADS_IN: Constraints are not imported with the design.
* q/ ~$ k& _' I) o* f) r236698 Report Unused parts in multiple parts package should be DRC+ i' W2 S3 A9 W# x- |
245193 export dxf height information when blocks are unchecked
3 `: o6 ]& j7 J254183 Multithreading for DRC and CM analysis in Allegro$ _* p" t: ~+ y! ?
282027 Problem with Split Part and part graphics3 L6 Z8 i# \- S1 c4 C" T, L
282507 request to import IBIS file directly5 [( v0 O( b& j) }0 m& f3 ?
283698 place by schematic page number window need enhancement* w9 V; s. P4 I* k) E9 ]8 S
288540 Schematic page# display order request for Quick place
9 u# ?4 ~& Y) z/ T2 k290641 Option to copy paste cursor value
( d- S% `# P# j; u. E4 w298081 Models from Funtion.olb need more explanation
  S( J' f! n* K' B. ~( c323813 Need negation and exclusion function in ADE reports
" T! `& x0 P' s8 q; [) Y/ a/ X341484 Wirebond: Tools to generate wirebond manufacturing outputs
; Y0 i9 `" Z1 `1 o+ F2 v1 J353212 Variant Name is not coming in Standard BOM
' ?* ]& C, {+ M360602 Enhancement to Show element on a via
6 S( F5 J5 K: k4 c* J9 h3 N362934 Enhancement for Allegro to utilize Dual Processors./ P& N: b$ M8 Z6 c" d; T* L
364850 change the font properties of Label Text5 ?/ P1 K; b7 V; {+ S, ?
367468 Need a real DML_PATH environment variable% G5 z9 ]/ R+ a3 X0 W
380714 Ability to have Power pin set to Not Connect& |3 y& N$ N2 `" F) ~% ?0 G
382860 Display parts and nets in different colors
0 Q, s* c0 e3 _$ J- _0 {384488 Add DEVICE and REFDES filter to Signal Model Browser* u5 N- H  {! V$ V, ^
391487 Ability to have user defined directory for storing distribution files for MC analysis$ w8 H! N8 ]- `9 i* `
420008 The renamed differential pair names are different in CM of ConceptHDL and CM of Allegro.8 H; Q* F* N9 h) s' I: t! c
420023 It should be possible to Delete a differential pair defined by SIGNAL_MODEL (.dml) on CM.
; l- y3 A# U6 T' R0 E8 d# q1 }420648 Need to get RF Elements to retain previously entered values! q# g8 J+ U; G4 O
429280 ARC is unable to load/save rules - submitted for tracking with Medtronic SiP benchmark
: F" f- E6 _9 l$ j. Z8 B430549 GUI for ADRC XML Rule files! Y5 X/ s5 ?+ {% I' o
430558 Store last used ADRC rule check ini and check values in .sip database
5 V: A# b5 C( v+ \- M452606 Can we have last plot as a default   I. g; ~4 I' s/ F1 }
454452 Allow neighboring/overlapping die pads on same net to go to same finger during wirebond add.
+ \: f7 {) X/ x9 E5 N$ H) P464056 Setup option to always prompt to baseline a new part) p# D" W( f" v/ |+ G
469378 Enhancement : Hide/Unhide feature for trace
% g& P/ r$ f$ c  c4 b475077 Schematic Generation Setup form is missing the Port symbol selection.  It was there in the 15.7 release.
8 a0 R  m- N, a! _475714 User Guide should mention that Temp Sweep is not honored in AA Flow?+ u) z$ r7 T9 {! }( Q$ l- n/ [
480843 Requesting ability to View > Zoom Mirror current view.
: S& f& u# B3 W$ s# @3 c2 x# k2 C484632 Request for Bond finger to snap to Guide in Free placement of Bond pads
9 l- ]7 y* v: m* M2 y, h  u490948 Provide a sketch line and text property form
* k  W/ J  X) P: z& x6 p6 h500550 CRef's should be preserved with the next run of the schgen in the preserve mode.
" c! M; K) g8 t/ P5 @* e505284 Enhance The ConceptHDL can set the color for $XR0 property.8 ^" }* Q0 C& S/ e9 z
512748 improving arc routing6 r$ w7 j! C* r6 E% ?5 b8 [
513967 staggered C-line via arrays
5 |. l# {) `5 g# c5 F. }; N! ]515333 Option to specify spacing between Components in the Generated Schematic
9 M# a8 r3 r- d+ Q525748 Why is MC Analysis Sigma value 1/3rd of 15.7 version value?
) x; @4 _- D* d/ F% i* D  `, _, l526818 Retain Hard Packaging Information option does not work for SECs.
3 i' h6 A7 L* x* x528391 SigXplorer measurement is wrong
1 u& m: m1 K7 u533844 Allegro password not encrypted in the .brd file.$ q  C: S' T6 U( W5 }$ `% d: u
536681 In the ADRC tool requesting a "Layer" option for Conductor to Package Substrate Edge Spacing) D' H/ C& ]$ r5 l4 T/ u
536948 Allow  sorting of power symbols* [- s' m$ y7 A$ K/ T1 z, [
539407 In ADRC Minimum Shape Check requesting individual "Layer" option
. _- `- k) G( P' Z& n$ r541145 slide command does not support to keeping the existing arc
  n4 k- l% V4 R( g541214 about supporting OpenDrain Model in Quad2signoise
+ v7 s1 G' ]" s0 ?542414 A function to force diff pair spacing to primary gap.% Z7 u8 K. h$ ]8 P2 ^, A9 S) b
542803 A "Minimum Shape Check Soldermask" entry is needed in ADRC
& x/ S* x8 y8 {8 r+ S! X2 q4 V& V5 J543470 Provide rectangle and line width thickness for Drill legend in NC drill Param5 q* C$ A- Z8 {" h3 i' ?2 M% p1 A
543766 Crefer fails to annotate occurrence properties to offpage symbols in replicated blocks, ~: L& Z# c% `2 c
545408 Cursors are toggled off when deleting a plot+ K& c8 ~  S2 V5 Q  I% ?& a9 [
546891 Enhancement: message improvement when expand design action in Concept; T, z$ J6 a+ E; e- Q# ?' C
546985 XOR function to allow to compare layers within different or same designs
& y9 G) r/ y  u4 [+ O- b548920 Add a document of which properties can be synced and which cannot be and the files required
' x+ _% X3 A$ @) S4 R: s553669 Add a 3D viewer to Allegro! b, E! Z! m0 i* i
555183 Wire Bond Report --- Report field should have save function for reuse
% o8 e9 s2 A* x! P/ f( Y556200 Need listing of DE HDL command names and switches.
  L" S' A$ N4 ]- @; [( t556883 Grid point for Origin to be highlighted8 T0 g7 m1 B& E
559638 Enhancement for importing height from PADS in allegro
7 K2 M1 L% w9 |  K8 N8 o559724 Request cline via arrays to be applied to diffpair nets$ ^: R1 @, Z- |! `1 W
560134 Show Element Customized Display
6 }4 Z" m  y$ U% [; K/ T) Q3 S563957 Enhance Color Dialog form Class/Subclass section to expand vertically when the form size increases.' u' X. Q0 i1 |  U
568058 Request to have component information available through the context menus, D0 ~, Y, Z( P8 R! C
569615 Enhancement to import constraints from Mentor Board Station to Allegro PCB
0 h+ k9 ?7 V. H  |569680 BOMHDL defaults to the wrong file type when html report type is selected3 y/ G% ?" }/ f+ [4 @
569784 Request ability to assign netname to via during copy, ?( C  c  t4 y& H% {+ t1 d
569863 User would like to set a larger default trace width! U9 `7 r/ ^" v4 c
570128 Enhancement : Packager setup for subdesign drop down) a) ]# \1 ^, C2 h2 A( u
570195 SiP - Provide option to create/combine BF labeling with additional text required for Bond diagrams
# R! F4 a$ B" X3 k# @570861 Unconnected mark does not be removed even after wire is connected to the pin.: J: C) J5 E" ^/ g9 I% N' U
575211 Web links in CIS explorer are not working when Firefox 3 as a default Browser8 z* A, L" g0 J$ r, O  h
577944 Enhancement request to have the drill legend for thru holes and slots to be separated without being on top of each other4 S1 B1 A% F- C- e" Q7 U& m5 ~
583630 Can Multiple Section pop up box be disabled?  s4 ?# M3 y; x, h' L' s3 }2 t" a8 A
583712 Ability to have string values for SCHEMATIC_GROUP property% j- |' j" Z5 Q$ m5 k# c7 S4 r
585904 Find a schematic page with help of nets
1 k& T$ W- {' n1 Y589512 RF component snap is 'too clever'( P. u/ \' Y0 \9 X! b
590246 CIS to Allegro flow to include or ignore constraints same as HDL to Allegro9 D/ q8 ^5 S  {7 X8 j
591306 Suppress RF edit window when changing RF Element properties) d$ X* I% i1 C& f% Y, {: e# v
591318 Use RF setup values or retain changed values in RF Element forms
1 R$ ~! J# D9 f- x5 D591443 Temporary highlighting is lost when using the Copy command0 e5 Y5 @% l- o
591450 Provide a dynamic tapering option to RF PCB Route
4 F: Z5 V4 j, z* k7 G591489 Would like to suppress RF Snap windowing around the user pick automatically- r. m6 G0 x& r, b4 p2 }
591812 Provide move options for the RF Snap command
3 W" c7 r4 Y" V1 E. R9 f591817 Provide easy group and element ID in repackage form
1 t% O9 {2 k5 V( Q: V* O* w0 M591825 Quickplace for RF Elements9 A' m  c: ?$ |  @2 ~) N0 f
591865 Request for more information on 'Other' Netlist formats$ c$ ]$ d7 r9 r7 D* I. Y, x* ~
596392 Publish PDF needs improved error messages for missing installation., l* K3 L: Q  t
596555 Request alias symbols documentation to include and clarify when necessary to rotate 180 degrees, `4 h& K4 L; G( e: o- m% O
596843 Cannot do global search after importing read-only schematic block
4 `" u" X& s9 j597808 Option to increase the default thickness of all traces in Probe- Y# ]* e6 i3 @8 m
599499 Plotting from within Allegro does not find path to stipple file
- l& ^7 h4 J1 @1 T: N, a: _  H604125 Manufacture>Create Bond finger Soldermask.8 k1 O/ F# y2 T, h" R6 _$ E
605023 Need rats by layer function for Free Viewer
# F% L8 i9 s8 T& m* z% f3 [% x605112 Dies should not be counted as conductor layers in Design Summary Report of SiP: G( N$ T' K; m% F
605373 importing and Exporting BondWires+ O, x% P. e( }* ]* a6 t$ _8 Y
609035 Voltage_bus part - Make pin number invisible
- i" H% Y, N( f# d$ k609561 Enhance Circuit Replicate to support coppers shapes connect lines and vias
8 W3 Q9 W' h, Y) b4 V3 {9 Q0 G2 L610934 Retain user input values in RF PCB forms4 A1 C/ v2 p  S0 \4 z) u  j# Y
612008 Mirror Rules need to be documented for axlTransformObject.. `2 q( ^  u1 u2 m, y3 Y0 M) G
613639 Update Documentation for "split_inst_name" property.
1 D, x. G: q" `2 D614345 Email facility for Design partition on Solaris does not work8 ?. j6 O7 K$ j4 P: I/ M0 t
615139 option DMFACTOR  documentation missing in pspcref.pdf( s; a' ]6 j6 {
615374 Retain Soldermask Thickness value in 3D Viewer Options, V% ]/ d* O5 \: a; h, u
615850 Auto Setup should honor device setup parameters if component value is null
3 p8 J" Q! G9 ?; ]* n615988 PDV WHen importing from Mentor does the browser not remember the last location of import0 [, v$ ]0 X# F5 |
616529 15.7 Design Entry HDL fails with Out of Memory message2 w& U8 B' W5 S4 s' a
616873 Uppercase characters in design name error should be improved
, u1 K& h: B. x( S' m9 R- V617976 Enhancement for a way to sort user subclass in define subclass form
0 T7 E& d5 Q9 v7 }( r620289 Server 2003 support information in pcbsystemreqs.pdf; ?/ u/ s8 B/ I# Q  s' @. P) X
620303 Enhancement: Shortcut key for "Select Entire Net"
/ q2 W% v' r6 r: q621054 Renamed net in netlist isolates components from the rest of the net./ [3 K5 H7 c0 `! f& E2 m
621955 Offset Via Generator utility should show a warning message if vias are already present.4 P' M/ h6 ]/ p- G  b4 [6 C7 x
622203 Requesting that "DFA Constraint Spreadsheet" icon be added in Customization >Toolbar commands
9 w9 y( i1 _  {2 u1 J* O+ e3 R623218 display pin names associated with a net in net Properties
0 O1 y* [3 ?2 |623908 Mirror Symbols while dynamically moving enhancement
( j9 E, U' P. g4 ~% `! Y624817 Display padstack name in data tips when hovering over Pad-stack& G; K7 O/ Q1 O9 F9 F
625733 In Netlist Report they are requesting square bracket vs angle bracket9 Z- _8 i" x! A% b- W# y
626605 Extract topology with routed interconnect to include via's in Allegro DesignPlanner, PCB XL and PCB GXL+ q$ s! h$ W" f; F( n8 \3 i' d$ @
626673 16.2 Die Stack Editor - Add option for DIE x y cords within DIE STACK form - shows rotation and allows move but% M& b' W) Z( q9 e" x) y# e
629008 enhancements for find command" C7 S9 q" s" Z+ Y2 {. c% Z# U
629548 Request an Option in Create Plating Bar where it may be directed to a different Subclass8 Z! ^- n* G: i& K* \
630949 DRC for bond wire to bond wire requires additional parameter "wire profile" to "wire profile"
  ~  B) ?2 n8 m% k3 @630955 SCM does not see design difference after update of fixed die/BGA in cdnsip
! ]/ a  Z  @% g) l630973 SCM should see the net assignment made in CDNSIP for Power and Ground pins' C9 V; m. _% D3 u
631609 Clarify how to generate a cref.dat file in Cadence Help& I9 I6 y& t! r  b
631697 Want to degass many shapes in succession with custom parameters2 \' p/ d. S; e! o2 ~& `
632754 pspPN and lib_list should reflect location of new models in 16.2) I0 c/ {0 q+ o' z. b& O
633440 Sensitivity not varying components correctly
  n; N+ d7 N5 B7 ]; o9 d2 q633842 Add note to docs regarding padstack quickview3 ~8 e1 p# d& `2 }- P
634350 Enhancement suggestions for pop up info boxes.# Z3 d& f/ w. M* t" Z6 v: a
634877 Export netlist with properties changes scope from global to local- A# S$ Y2 d& L4 ]# `4 D; c
635118 SKILL variable to obtain list of Classes and user defined subclasses in a database
1 [, N& R+ T1 [635233 Place hierarchical pin tool tip1 Q$ c3 j; y; P5 L9 b+ S) S  [
635543 Any command to get the current line/lock type information?
0 I" H' u3 z& Y3 }# E$ R$ j' }635579 Enhancement for Structured format in parameter file% N3 ^6 D) n2 H2 l& b) n
636930 Die Export option to create symbol either from schematic or layout1 t( S" q# d: s7 J3 W
637195 Allow for SKill access to backdrill info on padstacks
" H6 J  D! L1 w* Y6 r6 A" Z637768 Enhancement to assign different colors to different net based on a unique property
9 K) M6 p3 x* T5 i" J7 Q638455 Enhancement: Add some details regarding nomd.lib
) M/ ~, U- K8 W8 Y2 Y' i1 e' y638581 ENH - Press ESC button Spreadsheet window disappear7 ^' t$ l& \: n( V
638622 Add note to CM Spacing Domain Region worksheets regarding shape2element clearance
7 ^$ @2 N; e7 P( `1 z; Z" w1 C638910 Enhancement to sort the list of available vias alphabetically in the via list ?
& c" [" }. l& T  f5 T639630 Does the Net_Short property work with Modules?
/ l- B3 d0 `+ |* Q640262 Request object membership count in the status line and forms of CM.
9 Q0 I. ~" k6 \( ~640280 Provide resizable windows in CM and other apps% @1 X- g+ @( u$ R. d. j7 L
640668 File>Change Editor needs ability to go from GXL to Performance L or Design L.
' r  E) t( N% L  K& o642095 Ability to disable the Pop-Up description of elements" ]8 e( k2 k; N% K) d  P
642298 ENH: For license checkout detailed message& [+ I9 o$ w% v9 u& s/ g: e
642422 After Copy parameters from one part to other in partmanager forgets previously highlighted line
/ Y5 k, T+ w3 e' a1 J3 k* b642865 Allow format of hyperlinks in ptf files
8 i( Y3 c# l- i: v3 L642894 ERROR(SPCOCN-1993) is not documented anywhere in Cadence Help: Q( `+ ?- X' \9 q0 A$ R
643381 Add an option to ts2dml to allow user specified port ordering.7 X5 u4 ?4 [' f. v* I* H
643390 Request for a switch or button that would allow Properties to be maintained during a shape merge8 M( d7 P3 K( G% c' V3 ^% W" z
643625 Bond Wire export to DXF does not support WYSWYG
, h6 z7 y$ [# T0 G3 M643790 Include Associated Components in the Verilog netlist
' h4 F, U, r$ T7 f644216 Store Filter Row Data and Units Of Measurement in site-specific file.6 d, O% ^! s1 |0 M0 I
644248 Need a better solution to identify and handle unstuffed components! I  w& `/ i% I: s7 _
644350 Incorrect upper/lower case for axlPadstackToDisk in Allegro SKILL reference manual: B1 w) d/ `: s' \' y. h
646662 Enhancement to add feature to toggle on/off inter communication tool from within PCB Editor when using DE CIS.% p; h  H" ^4 s9 F8 {6 G
646981 about the treatment of NO_GLOSS property in Missing Fillets Report
. W1 V5 v) ?8 b5 a647480 global setting for adrc settings in sip via techfile( R8 R* {9 k+ g0 x, T, x+ j+ q
647617 Degassing not suppressing shapes less than size specified# ^  Z) o% `) _6 o- }( j6 u
648210 Request for Working Layer (WL) model in all tier Allegro tools..
' E% {, J8 j% o648218 must delete keyword "multiwire" from Doc8 k  V" F( Q# `0 N$ w0 N/ b' h# N1 T
648533 The cross probe highlighting between DEHDL and Allegro PCB Editor is not documented$ `* [& C, r# o2 v, s# c
648801 Stream Out issue for SPACER7 W' o, f7 O+ y
648930 If two PPT option set names match a given component which one will be used?
$ v8 L/ _- w% y+ [  d8 ?" n( p7 e1 P% T649603 about spara import! N/ F3 N; ~0 I; e) e  y% Y
649607 Management of SiP Technology File and Project Information
; |7 \: I8 G! r% s5 U. h% y( }, _649610 Management of Part Table (PTF) Files
8 s& ]5 y" w1 H5 i$ v649613 Management of Library Lists
! D, i# [! l7 r9 E0 n0 t652335 Tooltips clutter Place Part dialog.Option to switch it OF and ON) ^$ Q# y7 `$ G( m6 Y
652511 Unplace Component command* U6 {0 \( `, B7 O- P& j
652554 Enhancement request for Allegro to check the vias used to the allowable vias defined in constraint manager
3 T( F% y# U' n* X" u652939 Is there a way to predefine the values for Sample Start Height and Sample Start Length in Wire Profile Editor?
' r* L5 }! M0 R- L1 o& _( Z653027 Explicit RMB "Done" option is required in Part Developer symbol editor when editing text/ W( }+ x3 g% T& K2 ?( M
653359 Setting the $PN to # does not set the pin numbers to invisible when part is sectioned using the section command; O. G' e+ c/ b
653420 Enhance ADRC rule for Acute Angle Merged Metal Check to work on a user defined minimum constraint value/ q( j, H* {5 \
653471 Request for Die Text In Wizard option to Flip the DIE coordinates
4 h8 B! D  l1 F+ R. v  b7 u' S653825 sigxp_tier was not reset when installing a new product suite
: Q$ J6 A2 s) d) H2 ~657180 Enhancement: Tooltip for DRC markers
7 H& Z9 b% [3 [0 B657187 SI model delete enhancement
7 d' Y, ^0 G4 k% w! l657189 SI Model assign enhancement #24 k# |1 `* s/ O# \8 _  r
657501 Negative planes doesn't match with Film View* |) F( \% _: H2 v$ r
659543 Need a Report to show which Die Pins have no bond wire attached! P" \' s# W1 k3 _
659661 Function needs for setting the rotation angle in finger by group.
5 ?# ?- }& y( P  J6 O  |6 V! F661477 Color192 window sections to be resizable
8 P6 r4 B! g4 ]7 |; A  y662215 Please add the function of renaming net by batch command.) s8 z( t* k6 ]6 k
662325 Skill code example axlDBGetProperties.txt not correct+ q8 i9 u& _* A( a1 d9 {  p5 [
662982 When you edit shape, ministat should always enable shape" h+ Y: L3 `: b$ ]4 }
663260 Enhancement: ALG0051 message should be more specific$ s# V# e) b' A! @8 D% w- M7 ~, V
663754 Enhancement to create Device file when saving dra file on opening another design
; B* `2 A2 h0 F664240 Add CNVPATH in User Preferences to place default CNV files: n% H% w4 N7 N
665798 163BETA - provide graphical examples to show result of Flexible Shape Editor actions" X) k  a: U9 U2 X
666186 Enhancement FishEye functionality in Variant View Mode) r; a! F% }+ `: O
666768 Temporary graphics for modules / groups do not reflect true size
2 a5 T# I2 E. o& D666775 Update microvia to microvia DRC markings to avoid upper and lower case confusion
6 ?8 \/ b$ T6 x667773 Request for ability to set grid definition by entering simple formula
9 C7 w5 ^+ F- f( c2 E668110 Customer wants to enter the value of radius when editing routes.- O2 g4 ?6 m* H4 Y0 l+ T! M1 V
669373 Xnets are not formed correctly in CM. Up to 14 'extra' in a copy of the same design.
  R: N( n5 H" I. D# h669380 Add options for ts2dml in MI
. U6 N! s0 w- Y- }& L& {2 k669798 Add all 5  Dyn_Thermal_Con_Type property options to Via_Array.1 D# A- u6 `% G9 H& g
670775 Request to make the SKILL _axlSetDynamicsRotation and Mirror functions public
7 |3 M0 t1 L+ [6 x: W671194 Allegro not to crash when opening unsupported files  @" c7 ^4 [8 f# w: H# B/ b
671337 Request performance improvement to access DML libraries from SigXplorer or PCB SI.* N' E* Y7 {5 y% n  Y
671757 Handling of double quotes in HSPICE subckt.
/ Y/ |! K+ ^) G1 |672930 ERROR [DRC0039] Tap may not be connected with the bus Check Entire net
& U! d% o2 [& f4 o4 t9 z674666 Report the wirebonds XY coordinates" }6 k$ X! N' U9 v8 Z) x8 F
675118 Cline change width command enhancement
) W: M- U4 U' P# `2 q' ~675151 Insert comment option for database elements
, X3 R0 `+ {4 U( G675398 RF PCB setup should automatically point at the project file if Allegro is launched form a project manager
( G5 k5 Q8 P; H6 F! Y675551 schematic to sip layout fail
6 g6 S- ]+ s! a: X0 p676814 Signal Library command with Allegro performance license.
  S8 ~5 h4 G2 N7 s4 n676906 Add switch -regenerate_xnets to the dbdoctor dUI
0 |+ G2 p3 u) {7 Q* h6 v; `677983 about setting of ibis2signoise option "-d" as default
9 l, m" Q, o# C2 R, u  x678036 Request for a Physical design compare.
0 O: R) S0 F7 O7 r6 z) b678798 Identify DC nets command doesn't remove the RATSNEST_SCHEDULE
" t3 D5 X  y  h; u679926 Testprep fails with no route keepin. Message in testprep.log ambigious at best  C2 t4 {# n0 M
680586 Explanation of functions and macros in online help
# t) K/ r: [3 y  Q7 M8 x682695 Offset is outside or on pad edge. DEFAULT INTERNAL: REGULAR-PAD message needs rephrased! |" b2 ~, i7 F( e! M
682865 When using PTC format IDF files don't use forward slashes.' D, I/ U& b# [6 M  I6 j# a5 ^, p  M
684713 pin_count view needed for packages
- @& i7 `# x% F( U% e684796 do not delete all vias with DRC for via array
/ W/ Q( l0 f& [+ x8 ?686103 Replace vias evenly spaced apart, g, U+ }: }1 X' D0 g
686112 Add Connect and Slide keeps cline length
% s/ X/ t# }- n% x686122 Select objects by polygon) c  S5 ?4 D' l0 ?2 o% l1 V
687155 License for batch signoise command; J& v; h& x7 H/ ]. ]4 b+ f) x
687187 BGA Full stagger matrix wizard generation3 K, `9 @* I5 k4 L$ O
687201 Improvement in Find feature- l" A; u3 v  z8 l" S/ `$ x
687685 Documentation of new properties in Variables block
! Y# S8 v5 {' s688047 Include blank space in pin name as the illegal character in PDV user guide2 C" V6 W  Q& |* U$ K
688830 renaming feature discrete library translator
+ i" P$ z$ z+ L# @8 I689720 Need the ability to re-center Vis's in center of Pins when a Die is changed.& x9 p. t. q6 T# I0 J. v! I5 H( H$ X
695957 master.tag generated from the table design needs to contain the verilog representation of the sch.
. Q& j5 h) c! D: d. ~696661 Add ability in Offset Via Generator to add vias per a given Net5 e- J5 ]- x0 |+ N, N* c9 X+ z
696812 provide description for axlCnsPurgeAll() skill function in doc
4 \" M, s' T& x697824 Components not installed of variant design should not be extracted into SigXplorer.
% N" N  [1 C8 P" t1 T698097 Color Dialog form (color192) does not resize correctly
1 t: x3 A1 R& X" K+ N+ L( _. l7 n700262 Unable to add Signal Library Model paths in the Allegro Physical Viewer (part of the Allegro PCB SI -L tool)
/ M' {- d: t) X8 |700712 Defined pin locations are not used when using Die Text-in Wizard with default option Center pins on symbol origin9 H' y2 L1 v2 }; G
701514 axlCNSGetSpacing online documentation enhancement request regarding "bbvia_gap"6 v: p' g# A" H
702190 Request support of Windows 2008 Server Editions.
8 z1 @. |* S' N702613 Request SaveRefdesModelAssignments support the include original model path option.
3 w) L4 ?3 Y+ C: J3 m703905 Need Hot Fix number Info on Help >> About( O: Y; ]9 O. R- i! O
704594 Update symbol removes the text present on Package_Geometry/Silkscreen. u+ g, ]% D, m. L! r. w
704899 Split Bundle Methodology Should Include a Next Function
/ G) [; D# K$ V* T" A( {, O705601 Please make listnindex a public Skill command
2 @& ]! _( [: ^& }% F2 a705615 During Updating Symbol the text location and size are changed so Reset Text location is confusing0 b; c: Z# X% q
706165 idf import fails to expand drawing enough to accept text.
9 Y/ l7 Y2 D1 \0 E8 ^706457 Change type of the fourth optional argument for Mirror in axlGeoRotatePt to boolean" W- {& e5 S* q( O: c' Z
706463 Add optional Character in the starting of each line of the file created by axlLogHeader% B# U5 [9 _. V) r- S2 S9 j$ u4 a  M
706787 Fillet should remain when user slide the segment far from pin/via.. P* n4 P& \7 S) q2 T! A5 V( J
709119 Requesting a pull down menu with "Comp" and "Net" to be added in the Offset Via Generator0 R5 K9 m/ A" g, B/ u1 `' i
711837 remove the comma from the image of grid value separator) ?0 G' Y; ]/ {( |. L
714840 Enhancement: Anti-etch can be recognized as Void element.# ~" Y8 n: J, D8 s3 N  ^  C
715454 Option to configure Design Entry HDL for Cadence Help' l  ]0 g; e! H# B2 d) a3 {
715713 Enhancement for Wire Short Check during move feature* R0 z4 a' C( }) R" E% J7 u' Y) q# f6 R' p
716671 About the log file of the na2 interface.
4 W2 }+ U" k: _) J1 K717722 Pad designer  File > save as should have recent file name in file field, U  }. J2 \% y' a2 z  w) _) f
718431 Enhancement request to have DRC checks on negative layers.
! d0 w0 ~# X4 y; i# L719050 Log file should contain username date and time while creating or saving .DRA file  _/ C- U7 C) ^. o( A" ]5 Y
719514 Request length column be added to the Dangling Line Report
' X% z5 T/ F) `2 D720297 about "rip up thermal-relief clines"3 z7 G+ a9 W: O8 F
722346 DRC checks for mismatches in labeling Net
* a" f, ]8 k: v" F* L723661 Add *.pad in the File of type drop down menu when executing QVUpdate
, C2 d& d5 w. s4 W) |  x724832 Tackpoint move on a non standard wire bond -> *Error* difference: can't handle (2043.0 - nil)
" `2 r/ j$ k* {/ R& P726057 Request incremental DRC update when enabling DFA constraints.
/ w" W3 B' M& \) h+ ?6 K  b) Y# H728908 Add Color View Save and Load in Symbol Editor
& O+ [+ s3 x8 D% b, M% r: `3 Z9 B729947 User would like a metal usage report
/ G* g$ r2 M/ t4 V8 \1 O* E
9 a9 B. K1 X- W& S' q# M
2 j: h) f/ f4 MBUG CCRs7 }9 f1 l( d! n, N
--------
1 ^, H4 p/ R6 K7 C3 m: ], d# V; q1 F
2 i) B; |0 Z5 i5 ~' E$ {" k
CCR Description
- _% g4 i  p1 O3 s) V4 }3 U  O  M----- -----------
- C4 k2 D9 p( G8 K$ N----- -----------  Y6 X0 C6 C2 s1 ^. n: W- a

! D" [. _4 `& q% `# S8 [# p6 G10116 Add Intersheet references does not work in Complex Hierarchy% f# _5 k- Q2 x/ O* h7 X9 A
11833 Junction not automatically placed when it should be.
+ m9 i) O8 a3 ?5 N; p; J! ?- {- j16310 Simple hierarchy, intersheet refs not refering to H-block+ m0 ~6 }' n" M
19343 Request for intersheet reference to show grid reference zone
, Y8 X( r/ E3 N4 R22424 Intersheet refs wont work on imported off-page connectors0 Y0 R7 L0 r% i
34275 Ibis2signoise fails with legal characters in file
* d2 U6 S) d6 l3 ^9 `( H85735 Cref annotations of the P_ID+00 Bus were missing3 ~( `3 u: l1 p) N
134692 DDB_WARN: POWER_GROUP prop. not allowed wrongly coming
# I, p' ]5 ~% D. }( H0 e: y199343 Stackup-Aware SigXplorer5 v8 f4 }" Q6 T6 b2 C. W2 V
207620 Part in MISC2.OLB has incorrect pin out
5 f" ^. ^# v$ N1 O) O' S2 N  x270347 Changes to AXL SKILL must be Documented.
$ ~" S: }- u' q283839 lm117 dropout voltage is too large0 J2 F+ L! _3 d5 w8 G
296826 Variant view displays library property) P# d4 P4 B2 V1 U( @+ w
299384 Part rotation resets the text to default position4 @- e5 X3 Z: }2 K+ K+ h2 x
328647 Replace Cache takes time for network libraries$ }) ]. F+ y5 Q5 r% D
340323 Dynamic shapes need same tweaks in 15.7 as in 15.5.1 to fill
+ @  V& E) P8 x" k* \341035 Dynamic shape fails to fill in design that has cline arcs  R1 P7 Q  ]2 A) Z
390692 Via not getting transferred through the Area Constraint from Allegro to Specctra
$ ?. f5 P4 a, t0 L% \2 s- p405611 Environment variable for SIGNAL_INSTALL_DIR is resolved.
' n% E) N9 I) d1 m/ ^3 d428261 spaces at end of pin name Could not create new pin inst library correction utility) D2 a* @/ n0 @4 w. x
436908 The color dialog window will loose the vertical scroll bar after being minimized.
: J# l3 f# i, s0 U+ h/ K% n* z* t437369 Menu selection of Export > Libraries fails to issue the dlib command.5 _, e. S& t' J+ `' ]( b5 ?  Q( B
462783 Busname is too long5 G6 i" z# h$ ~: U& x
495671 Unable to add the signal stubs due to the overlap between SIG_NAME & VALUE Props./ X: Y7 g$ p6 K# t5 w
509393 NC drill legend copies null nc_param.txt to current dir.
& ~3 X6 F2 @9 T  i512809 Window Prt.part.ptf shrinks by 30% and I have to maximize it.4 l0 y& D* `& k
520802 Global Navigate Zoom to Object needs to remember last setting$ x# n8 T0 F9 K9 T1 u9 L
528686 During text edit the cursor overlaps a letter rather than in between: F: V3 j9 U0 `1 q9 E" L0 }
531555 The diode BAV99 from library works inverted in compare with the graphical representation.1 h7 H% R6 ]& e% z9 [1 t! b
532603 Specifying TC1 and TC2 properties does not seem to have effect+ s, }# b& K1 ]" Y
547339 CM-SigXplorer extraction shows different topology in DE HDL vs PCB Editor
* h+ @/ r3 [! `548143 Dynamic shape on Etch TOP will not void properly.
$ h- ~& g! W' m5 H" j550657 Importing registries do not setup printers from MWcontrol
% `& `3 t( B2 \  B* a2 C552227 about die export padstack  layer mapping9 W  Q& H& g0 F4 ^1 _  o2 e
553035 Cref Synonym and Netsbypage reports do not match netlist8 L- H7 A. W9 B4 R8 ?
558164 All variants are affected by function regardless of being called for  @; `$ t7 [6 y( W  p  `8 d6 S
558692 Memory leak problem in loading marker files
# h- u4 `3 `+ W565681 Filling in values in CM by using ctrl+c,ctrl+v and arrow keys is not working as it should.
: V# k9 d1 l; _9 m  v" ~& A6 S5 P" e567606 PDV selecting pins in symbol editor shows pins off grid during move5 |/ z9 X* ^! A: ^! O4 H: r
568049 Genview crashes
6 X2 d3 u4 H5 o. x5 J* S, C575353 Large box displayed with place manual-h and no RefDes variable set" Y3 S1 ]; y" [% M9 Y( f1 k) P1 B
581848 not able to edit Padstack Boundary" O$ z; `" L; J# z
591847 Add Intersheet References does not work on simple H design.4 o! t$ F, ^- O5 t# }
592381 Physical Min/Max line width values not check on internal rows or forms.  _* x( b% \" R' N- L5 u# K
593076 Cannot redisplay an invisible OFFPAGE connector's name
- G* A0 \: e- h5 t# R3 i) i; s, Z5 S5 n' i598038 Detail button of Markers window with 16.01
- u: n" N- y4 K6 y601415 Allegro Design Entry Tutorial corrections.
: g8 s# e9 P. @601531 When using the place manual command and rotating part a ghost image is left behind7 ~4 F4 X, r- F# e6 B% P* u
603181 Formula to calculate the Actual Temperature for Smoke is incorrect./ j  E' C* r+ x9 G! `+ \( `' }0 t# A! d
604965 need to document how tcl cmd addComponent handles property values with spaces( R, b; ~9 p: R! U% ^' B( T& U; C
605843 Aliased nets do not fully dehighlight when next net is highlighted2 Y! t! \- P  C4 r! b6 ?" N. J- H! Q
606493 Targeted nets are not remaining targets
$ U7 k4 ^0 ~$ g; b608150 TestPrep generation is creating DRC errors
3 a( H7 N0 G4 |; D4 X608787 Missing Constraints Report! \! ]. c" x2 ?
608942 PDF Publisher output misaligns text in tables: }. q$ j) K7 f
612511 Error in Flow Tutorial regarding checking default user units' `2 y. t+ m  ?
612982 VLIM model giving error that line is too long
1 t- l4 a7 E# O0 _) o) e- N613194 Adding wire bonds with current selection does not yield DRC's, mismatching Allow DRC violations option.. \5 [" i" }/ X) B) C+ A
613738 Variant BOM report lists identical parts in separate lines due to POWER_GROUP$ w7 {6 F8 C( n) {8 |0 B, |6 g% u, Q
617146 Symbol fails to place through Component Browser$ K8 Q* x3 I+ V" I0 Q( ^
617327 Change root operation results in SCM crash
: H8 ^/ c) f0 ?2 E% Z* F+ i* F618150 Property Editor Functionality
2 ?8 f8 C; X5 m3 [& R/ i618617 Enabling strokes requires checking/unchecking options boxes0 N( \- o$ P9 C" p. X
618771 PDV error SPLBPD-382 when importing from APD.
/ q) |5 Q4 \; [7 k5 h619053 Diff Pair problem with creating them in DEHDL.
) O, _; R1 [6 x6 O1 ?619849 Hierarchical Blocks Loosing reference
$ U6 L  Y# {* S: `; @( E2 L620001 Measurement's Maximum range calculation is not correct4 o! [& N) P! Y4 E' [
620343 Bogus error during schematic write; r/ E6 ?- J- Y7 y3 i2 D
620826 Changing the units of dimensions does not work
" G; O4 g( S1 ]3 u1 [# m% _) r& J0 \621163 Ambiguity about the how is the ?start of the wire" defined in CDNSIP for ADRC Wire to bondfinger optical short
' F' u0 J& f8 [6 ~6 Y) W$ l2 N% R622263 Drill Customization sort order for oval oblong slots should account for Size Y$ p* S! {7 J, R9 x5 _
622583 Allegro produces erroneous error msg - symbol not found when the placebound is too large for the board.* X8 p8 t# s. ^* ?. Z, \
622692 Why is VGSR negative for N-channel MOSFETs3 k6 o; S! I3 j# R0 @% f; s1 ]/ }
624378 Device file content conflict
# l! |6 r2 A* x( ^/ @8 l9 `624492 Model Editor finds the wrong model definition for BAV99
7 ]- f  c2 o, |0 H/ F. Z# e625462 Symbol pins Property are lost when once stretched+ q9 i& U$ d6 `+ H5 ?
625519 hspice_mt is not used in Channel Analysis simulation* `7 }1 u' K# S9 n2 {3 i# b
626674 Allegro CDS_SITE setting don't appear to match documentation9 I/ e$ m% f8 e0 b
627018 Find Net in instance mode displays twice0 C8 n0 w1 f, F  E3 |& k9 K, c1 j/ q# D
627864 EDIF c2esch crashes
$ Z5 l, a2 S+ B3 }8 o628077 Degas not voiding correctly
8 B, m& z  ~; P% [628265 no "Unused Blind/Buried Via"Report in APD products
( R, n: ?$ t: _3 @) [/ u2 Z628845 Markers> Packager menu is unselectable even after pxl.mkr is created.
& X/ l" v# m% \- h6 Q1 B( Q  r& p4 P631344 Mouse Wheel Scroll misses the "along with the Control Button"2 F4 _0 P4 i& t5 V1 D) @
633130 The Verilog netlis is wrong
6 b  r: l6 X6 Q1 ?; Y633223 Running skill from a HDL script causes segmentation fault.
( X! {4 W' l- f6 J* V: a8 s" n633473 INPUT_SCRIPT inconsistency when removed from .cpm file
" Q- x. y: o& o634075 draw_etch_outline doesn't work for circular shape/arcs. M9 S8 N0 F2 n% |3 c
635779 Allegro OpenGL distorting text at certain zoom levels
, K- k2 v: q! w: i% W636215 Allegro documentation for Export Parameters is incorrect! d+ a1 @3 D/ u- {, t/ E
636688 Signal Model Assignment UI and Find filter association is broken
4 B! a  s0 s3 W; a# j9 Y$ t; L636819 Documentation wrongly indicates that DFA Analysis in unavailable in XL' I$ h( y  p  ]  i; t% r, z
637379 No column for ROOM shown in Constraint Manager* A/ M9 @, E  W& \) I
638140 Intersheet References not offsetting relative to Port4 X; R3 V. W6 |$ w0 h9 B$ D
638670 Testprep parameters - padstack selections - Bottom Side replacement text not entirely visible.
4 m; R' S" r2 [2 G" F, m638987 Change command hangs on customer?s database5 @7 t9 ~$ H4 e2 X
639052 Database Objects Preventing Layer From Being Deleted report fails to run
$ ]" g4 s. g8 q: C3 o639698 HOME variable defined with %USERNAME% doesn't use value of variable.3 I$ L& j5 T. Q. D5 J1 |" Q' U% i
639829 After setting Zoom key(F10) to a new alias Tool Tip is missing the key number' P. S3 d2 D4 e+ P
640127 Correct IDF documentation regarding UNOWNED objects, ]. |2 D: B  ^0 B
640293 performance issues with scm and large pin count devices
+ c4 X" }* Y/ }1 y0 x4 V640314 The number of menus written in DE-HDL UserGuide is untrue for Unix/Linux users.
8 u8 ?7 H* m/ I" u641503 Stop running the VAN check on a PLUMBING body symbol in PDV
& H+ |: \- U# E5 I' N- h0 I6 t641676 Incorrect link to assign refdes help
6 B8 d& t* X2 s642053 Drag Connected Objects icon is always display as on
7 N% l' g3 q, _8 S& \642299 Switch the windows mode by set command8 ~; W6 }: n" q' v. [. R9 i/ L( j
642436 Save As symbol in part editor is not working fine
. y* Q* e" |. {1 h4 y) |* d6 }642713 Materials are not refreshed when material name have only numbers.; t3 x% a( P1 c% @; i
642873 Dynamic shapes out of date message refers to Setup Drawing Options
1 O  R& N- _7 Z# u643721 Attributes with Null values in symbol.css files are removed when saved in PDV# y1 m4 m3 g7 I; @& p" f
643949 Can not create Region-Class-Class for same net class.
0 i, W" K2 b! s/ l6 I/ p644016 APD crashes when creating a tile from LEF file
6 J' m- P) `& H# O644733 Import reference text file gives incorrect results
) G! t6 r* K2 c/ T8 b+ s644879 Change forms to enforce naming of lib.defs file
* P0 h% z' Z, F% j" y( [  `645046 SG1525A PWM model is reporting unmodel pins and producing incorrect results& N# n3 I2 e& }. v7 i
645427 The save button is not enabled on changing the line width9 b' c3 i, {7 @; L
645996 con2con fails to parse ppt file correctly
# i4 A$ I; N5 t7 |: t- a646175 Please modify the limit length of "Allegro PCB Editor Limits" correctly.; t, p  A( |! r" L
647555 Drill Customization text Non-standard Drill is not readable.
6 ^" R  k/ `% H# I# A. n8 d5 z- V647628 Annotate Type should be removed from PPT Option set files and documentation( L' e% F# \4 n5 ~2 ]: A
648443 Launching SCM without a license is not reported in debug.log
( w2 |) n5 x3 ?$ s5 X* L649222 Silent install adds extra License Server to CDS_LIC_FILE on the client4 f4 p6 o% K7 B, `/ e% l
650558 Die Pad layer changed after refresh padstack
: x6 e/ a; o, F) s5 g% n650997 Incorrect Pin Shape in CIS Explorer Footprint window1 w5 o+ w! T6 X; u- s1 i
651000 "Wire length over parent die" violation is incorrect.5 Z& B) t" a0 C3 Y( g+ b
651153 Results for imported CSV inconsistent in PDV
! c/ \+ Z' P* h* A651521 Resizing the display color visibility dialog box corrupts the display
" F# P7 m( H8 _/ g651526 Parts are missing in a advance analysis library list document and font size issue
9 K  o, ~: m" g9 g) G2 U& T651532 Scroll bars disappear after minimizing the color visibility form
! {, O) V8 n) Y' Q4 K3 a652050 Append waveform does not work in 16.2 for .dat files created in previous release with import text format
0 y6 Z3 t( {+ B' N$ f4 J# w0 O652904 significantly low performance issues when using edit interface to delete ports of block; I/ D. w2 |& F
653067 Incorrect warning SPMHNI-198 - Pin name is not legal and will be replaced by `$#?* ^; H8 n3 i5 N. G9 O# r) b' \
653784 Off-page connector name change to internal starting like "I12345555"9 o- q% U- q: F
654580 Save As should update lib.defs without executing the edit die operation5 O6 z& L; I; C
656282 BGA Generator adds outline and RefDes to wrong subclass) \6 a: Y% F1 o* H: S- U
656723 visibility of clines in 3d viewer needs ALL instead of just CON field in layers, |" |, M% b* `( d
657836 Text crop on User Preferences Editor form9 `/ g7 V" ^# J; _8 o3 a' u
658347 Rule Continuous Soldermask Coverage Check should not work on Cline Segments
. O  ?* `$ g  C, w5 C659437 Move group fails to display anything with Open GL enabled.
+ G1 a- E; E; y5 g" X1 r660937 Import techfile fails with etch on layer yet layer has no etch$ Y) c. \5 |9 d( Y9 q
661369 Importing design fails with the SPCOCN-1158 error when DBL_STR_LEN 'ON'
3 E& {, L; f5 U* W( b- b661754 Hyperlink publish pdf to correct page but wrong grid location
5 d) P* a1 u  q! o$ O662622 Export Physical reports error Output Layout Filename contains space  ^/ M6 R" T/ z/ B# o* V
662918 Skill code example for axlReportRegister does not work
* C  w, X, d6 N; R662971 Moving Bondwires disconnect bondfingers.
. n6 L7 m- l+ u% O5 |5 T663088 Cannot add connect to a C-line in Etch Edit Mode1 T& a0 j' u  j6 Z  A
663220 IMPORT_HFS_HARDSEC_ON_SWAP_PINS directive causes error on save in DEHDL# U% }6 G7 d2 C' A5 L
663726 ?Each? menu under RefDes is missing in BOM HDL user guide
' H3 f4 P" ?  `1 N, I4 T5 r664764 Material changes when layer type is changed! s$ T9 o' M! a4 w* D' p1 T
664900 Project manager User Preferences Editor form has text crop." t4 s- y* [$ |7 s: B
665236 Unable to import a Quartus-II version 9.0 pin file.
/ h  y) D! ?* {% \665389 Spread between voids not working for customer design
9 a$ Z. L3 ^  C/ F- N& f665413 In File> "Import and Export"> "Import-ECO pin table" the NEXT button does nothing.
- b6 V" u  q8 P: f, S4 a665451 Import - Part logic - information popup window has incorrect user preferences Editor Category
9 o) o% g- s. `. M% s, C8 J4 U/ Z665661 Wirebond Die Escape Generator failed to generate Clines  h1 Y+ Y. W' ?. p2 g' D
666099 Mandating at least one symbol with sizable pins for using size..1(not for size-1..0) SPLBPD-310/SPLBPD-309 on reload+ \; b( R. F$ |4 Y
666667 Relational Table View Browsing Issue4 j9 z# O+ P- U; v4 p8 k) p
667286 import IFF No Component Shape Line Via found in IFF file.2 `/ Y4 X$ c& j6 r( h$ k
667751 db(v(out)) and vdb(out) gives different results for FFT
! R: J4 p5 o- {+ F* g6 f( C668080 Improve handling of curved routes
4 ]4 V9 D4 o8 |- s4 B& C5 Y# m* l668393 Dielectric constant or loss tangent values do not update when changing conductor
  q4 j4 q  J6 G668876 Text on the Add button is crop on the Edit via list form.. ], }8 _2 l) A6 G- x
668892 Incorrect Parallel Length data in parallelism report3 x8 C! c% J& p  m8 l5 p/ x
669206 Parallelism rule causing significant performance issues during DRC update
' V0 U6 k1 J: ~; s8 i669238 Unable to use permanent highlighting for groups in version 16.x
1 U+ R! j! D- }& f5 k669323 Allegro PCB SI User Guide Doc page 229 ignoring vias needs to be updated. o/ C) \( }, H5 G, F! E+ r
669336 Error in documentation of DE HDL Reference Guide
6 i  K( R7 E* i670874 getVersion() function not reporting tool version
+ K' q7 x" n. G& e$ F, s$ ?671811 Allegro extracta fails with more than 10 output files
/ O" c0 `( [& E. Y$ `) O, o$ V' H672420 User defined property added to component instance is a function property in Allegro
( @$ R8 i' s4 [' V672614 translator converts the symbol "\"  in the original Spice model to "[url=]\\\\[/url]"! h2 q! w$ R# t- s3 X6 Q  u! }
672615 Translator generates 6 external nodes should only have up to 5 nodes* s& P  l/ n- _; [7 y+ F
672618 Translator generates statement in the dml file: Language=hspice causing Spectre run errors1 o3 G$ O) V( o9 x
672715 Steam_out takes a long time and then fails but the .log file reports a successful export
9 I4 _( ^: |5 c& P/ I# `673279 Same characters are listed as both valid and invalid in naming rules.$ g- b3 U& ?9 A/ F- \
673410 search by net name is finding electrical3 ~4 t1 ^7 X# \
674058 Incorrect Variant Report
. [6 u- b6 ^  r5 w" L& L1 \; x, r- j674291 Library Explorer fails to start and I receive a 'Runtime Error!' pop-up
: ~1 o* W' z* q1 a  V+ M674555 If the DSN filename contains spaces, autobackup will not write any DBK files to, L; e# Y! f# _1 c% A
675192 Adding a second BGA caused dsa_api.c to crash
& E( `; V' M7 P. s+ n675231 SiP Layout doesn't handle ! characters in port names from Verilog and OpenAccess.. k" U* S% v5 ?) E: H: k0 v+ A
675562 axlWindowFit() documentation needs to be changed.. W! n( {+ p/ v3 b" ^) m# G. a" f
675783 SiP Wirebond moving a BF sometimes results in the BF placement on the guideline to become unplaced from alignment option$ P7 g3 Z' V9 ?& z2 m% \; _
676201 Cross section impedance not calculating with single license
2 M% j0 I8 J' V& ^: f- c& e0 ?676601 behavior of launch product from library manager7 D5 @( B# w& }" W
677582 mirror of die component on sip designs( t7 A2 U& P; v5 n% J4 K; K
678013 Error: Symbol not found, though symbol is mapped in psmpath
8 x8 t: T) l& j678427 repeatedly placed symbols has strange instance name7 o( f' M9 L! Z: J0 A" ^
678538 Why derive database does not transfer the Schematic Part property to CIS
3 h. T" Q6 E9 q678814 Spin a temp group will not rotate the symbol+ m; e8 w% E3 V
678851 Difference in lengths in 16.01 and 16.2
5 S6 [, X0 h3 y* k6 `678884 dbdoctor fixes corruption and then it's reintroduced4 g9 a# V5 U* \& k2 ^
679224 dbdoctor states it fixes an error but the error returns, S, y0 `8 o: U, b3 f
681197 Report generator Hangs Up Allegro PCB Editor) W" E# e+ n+ g
682135 Justification of $PN placeholders not working in 16.2 release. Y2 Q: j2 g, {- Z  `
682204 Cdsserv.exe and cdsqmgr.exe crashes using 16.2 release on Windows
+ H1 t( q# M% J" [) P- ^682331 Incorrect reference to the middle mouse button.# O9 {9 S$ N" N3 S# I
683146 export variant path appears wrong in output folder while two DSN are open simultaneously
* M+ i. m, l1 c* i: M8 _683182 DRC0037 shows incorrect Alternate Net Alias.
3 B  R/ J+ O$ K  O3 U7 _0 m  Q3 v683379 ERROR in Measurement ConversionGain_XRange
# D9 w# l& ?- K' `684180 Sizable pins and vector pins cannot reside together in a component.. Q- o$ P! r$ b' b. H
684661 via array created wrong results
7 L/ S. @6 W4 F) u684700 via array can not be placed on both sides of the cline
3 i# [/ @" \* Q. t7 b684912 16.2 documentation is incorrect for axlDeleteFillet
* H0 Z8 d- w  G  N: Y( q) h684915 Incorrect mention of creating graphics template in the PDV user guide. G/ R# J! R2 I( ]- s: Y! {
685685 When the customer tried to merge shapes, they disappeared and  do not merge., C7 i. _4 O# G( Y5 ^9 ~' m
686338 ERROR #8012 Database Operation Failed with MS SQL database
9 ]/ N* @4 v; F- d* J' _2 |686560 Changing pin group property after pin swap resets pin numbers) M! H& t$ }& m, @
686736 Load property does not propagate to the associated MECH part0 ?( O$ E, x6 r% A2 `4 Z; E9 J
687008 ERROR 8020 after removing Place Icon1 R2 c: `, z2 m# j
687074 Part disappears when you open it
. p: t, j+ _2 X  S687354 Not able to create allegro netlist 228 ERROR(SPCODD-228): Cannot package
' J, K8 ~& _; o+ W: e5 R+ @$ L687385 Publish PDF outputs the net name (with underscore) overlaps with wire.
' f+ z+ s9 Z$ N- j% a  ?% Z687708 Smoke deration calculations for Capacitor0 x1 X& v2 [2 Z' E6 Z
687715 Getting Warning TJL will not be smoke checked, x6 u1 d) z7 c8 u: b; _8 j/ }
688606 Inconsistency in synchronization between bias display and icon( X* c$ Z0 R+ J+ |- {. a
689542 Comma in ESpice model name causes simulation failure
( k' `' d* e1 f: H/ q/ H690112 Ignored nets are displayed in simulated crosstalk worksheet in CM# J# b. D7 w' R6 A; a5 x9 g5 c+ L& `
691668 Stimulus editor hangs on doing change type
, S) F5 y$ u9 a5 }. U691740 crash when setting coincident uvias in CM beta testing 16.3' I! h3 V! F( z6 q, ~) B/ _% A
694139 Case difference of net and bus while generating FPGA netlist
, s9 y* b- J/ ^2 }& Z! d1 z( B694716 Waveforms are flat when using IO b-element in HSpice0 t  m4 [: L7 D- t
695109 Incorrect Diff-pair topology extracted by Paksi-E field solver
! D/ \( ]) ?* M% H! M: `* X) U( s695431 csv2ptf fails without providing any error message5 v; @" }# I' G: }% T
696273 Shape disappears when updated in CDNSIP 16.01 and not following the constraints" `! a# e+ B3 J5 w% Q3 y
696534 Pin Visibility check box doesn't work while creating part from spreadsheet editor
0 m* b6 {% H! o698494 Shape not getting filled correctly6 e$ @6 a  v0 A0 z1 f. K: U7 N
700160 Error: TVCurve must start at time zero .
5 a% i5 Q# T/ j7 p2 j700644 Allegro Crashes on doing Zoom In+ D/ n; c: F, }9 G
700725 Create Fanout with Via structure add structure from Top to Int. for bottom pins
+ \$ v/ l" C' A9 d3 M' h701128 Inconsistent warning message : TBreak (Tknee)is less than Simulation Temperature& q" d( G3 S4 z7 H! K: N! r, ]! k
702557 Incorrect Behavior with FSP 2 FPGA Option License/ W1 g% v# l0 f" d' U- t1 S
703324 Cross probing board DRC objects to CM DRC spreadsheet fails to zoom in( ^/ N: Z4 g3 q3 X
704268 remove ARC and TOGGLE rmb options when in add rectangle or add circle command
+ W2 h1 R* ~7 a2 F704475 Allegro SI change editor to Allegro PCB XL causes menu problems: @) B2 I8 U* @
705902 ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor/ c# i$ I: ~4 m
705903 Cannot remove a matrix view after modifying the connections8 N& I/ r( Y) S2 W- z
706169 IDF in error has spelling mistake
, n! {; Y* @; V% F706613 Diff pair is not extracting properly through design link.& l* N! ]: M9 h  |
706729 Import properties fails with ERROR [IMP0020]7 q; [8 W, P; w( D1 \9 O1 Y4 S/ ^/ t( r
708134 Place > Manually command menus not refreshing the Placement list$ r2 i) k+ L* q" C2 R
708145 Creating a netlist with Rev. 57AQ is not formatting correctly2 n+ M2 j" A: y6 y
708634 Shapes getting incorrectly displayed in 16.2* |& `7 x1 x% `
710279 ERROR 8020# Place component operation failed.6 H6 M/ k8 Y" W
710859 Unable to create Diff Pair from Autosetup
" k: |, Y6 O# R; k711739 selecting one component/symbol of class IC can move unrelated component due to incorrect group membership." |% V- Z* p* \7 W
712299 Internal application error while creating new design
. x' U8 N( E4 X1 E712898 Netrev should not read PARENT_PPT_PART property value while importing the logic, due to which import logic fails
4 ~7 X, v3 t- ^' S$ M6 n1 S# r& V8 k713465 Problems with dynamic shape creation over routed full-arcs diffpairs, V/ J3 h$ A/ N; S: e/ ~
713480 Display issue when adding a custom property to the first bit of the bus.
  P4 H1 @" G, c714072 Error while linking database part2 z8 |& q; ~2 I2 Y. {9 Y3 P7 D
716097 Specctra is crash during route.6 Y1 _. U' j2 J1 p1 N) K3 V. ~
716212 PACK_SHORT property gives package error for visible POWER pins
& A; l' w; m9 h9 k5 p717484 Dynamic shape creating voids when moving a symbol
3 X3 j; B! t0 b  ~718151 Geometry not selected when we click tab for selection filter in pad designer
# w3 B. r+ M$ I* R$ k/ p; z; e720092 Difference of behavior for slide for segments in options tab & RMB options0 i' y" X1 L0 K1 Z" r& P, S
720191 Delay tune cannot keep the Gap if the diffpair segment is diagonal.( G) \& u1 z* X/ U# O
721415 Two buses are connected without a warning when moved on top of each other( ?# v3 h* W# Z" o& _
721938 Cross-Section open error8 ^' J( d* k2 @: [
722997 Hyperlink function does not work if zone info. includes hyphen. i$ s- _* }6 ?  n
723146 Pb during compilation using predicate getFileStrings
) e8 f' R0 e/ a% |# @4 w  }' Z723159 Typographical Error under "Synchronizing PTF Information" section8 O3 B, L& |( n  d
723235 client install results in incorrect, redundant, and problematic cds_lic_file variable# Y- ]& T0 |5 A2 a, h- S
724414 State Wins Over Design does not reset the subdesign_suffix block values
- I/ K3 a/ l# P* ]) Z$ n724969 Allegro crashes when using place replicate function4 k( b7 l* t4 v6 G4 d. E% u
725852 Impedance has little difference - BEM2D
5 R* w1 I7 @4 P( i0 P726731 SiP - Wirebond -> Edit -> select bond finger -> RMB Change characteristics results in bf not following snap/ c$ G% L' |6 v* h9 o
726763 crash during logic import in Allegro CM enabled flow
; [3 h5 J! g) O+ Q0 r0 `727663 Remove Subclass in My Favorites (Color Dialog) doesn't refresh properly; T- a. q; z+ {' b
729496 Build error in 16.3 and 16.4 cdnsip.exe
作者: osakau    时间: 2009-12-9 14:34
updates so quickly !
作者: partime    时间: 2009-12-9 15:00
有啥好期待的。allegro越来越像protel了，庞大，低效。
作者: 黑月    时间: 2009-12-10 08:46
如何下载？？
作者: pcbdesigner    时间: 2009-12-20 12:40
allegro16.3在HDI设计上确实改进不小，不过自从进入到16.0以后，操作习惯与设计效率方面个人认为还是有所下降，总的来说个人还是比较看好Cadence。



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