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Orcad Capture CIS 导网表问题,求助!

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发表于 2009-8-22 23:28 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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本帖最后由 whb3103536 于 2009-8-22 23:30 编辑 8 d. @9 `# _0 U4 e3 X

8 S6 B' {- Q0 c$ [3 g1 H. O$ O各位我在用Orcad Capture CIS 16.2 导网表时遇到一些难题!如下:" s" J. J; a; M3 ~3 ^9 J4 W7 h
# m0 m- J- X9 ^3 g. w+ E, C2 J' Q
********************************************************************************6 V9 @4 z. O7 t. k1 V
*
6 R$ i+ v' L9 i$ ~3 x* Netlisting the design   Z5 |+ q; I8 R4 i! F/ w' f
*9 u( W0 e( b2 D6 }+ x
********************************************************************************% f9 @' E0 W  q  Y% _8 e( y
Design Name:
2 y% y+ f* q! I+ s6 {% S6 ?f:\work\g-plus\g120\sch\g120_allegro.dsn
: w& a0 I- X/ ~$ m, hNetlist Directory:& N# X+ f9 u( _3 m- H
F:\PROJECTS\CADENCE\G120\NETLIST9 d7 v$ \7 W: L
Configuration File:
  w+ u# G) S6 LC:\Cadence\SPB_16.2\tools\capture\allegro.cfg
; x  ?' i# y$ c
Spawning... "C:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "f:\work\g-plus\g120\sch\g120_allegro.dsn" -n "F:\PROJECTS\CADENCE\G120\NETLIST" -c "C:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
. O8 @( f+ A  i+ ~8 P3 Q$ g#1 Warning [ALG0016] Part Name "BATTERY-CONNECTOR_3_KBC23S3M_R_BATTERY_CONNECTOR" is renamed to "BATTERY-CONNECTOR_3_KBC23S3M_R_".( N1 ]& C( Y6 s) Y7 g( O
#2 Warning [ALG0016] Part Name "SCHA1A0101_1_T-CARD-PUSH-PUSH_AC0200-030" is renamed to "SCHA1A0101_1_T-CARD-PUSH-PUSH_A".
  u0 |4 a# b* j9 r% a" T( r3 h#3 Warning [ALG0016] Part Name "CONN FLEX 5_FPCKEY_5PIN_FPC_KEY_CON" is renamed to "CONN FLEX 5_FPCKEY_5PIN_FPC_KEY".
* g; @1 _0 `8 n7 K! v0 t  y. b  V#4 Warning [ALG0016] Part Name "SIM_CONNECTOR_3_AC0100-063_AC0100-063" is renamed to "SIM_CONNECTOR_3_AC0100-063_AC01".
. s3 e5 j) R  Z% U  P4 ?' {( C- V#5 Warning [ALG0016] Part Name "CSTN_0.4'_C15DDS29_CMC1P4236-E_CMC1P4236-E" is renamed to "CSTN_0.4__C15DDS29_CMC1P4236-E_".
8 M: |& O4 n; ?" W" h#6 Warning [ALG0016] Part Name "GL826 LQFP46_3_QFN46_GL896-LQFN46_4.5X6.5X0.66MM" is renamed to "GL826 LQFP46_3_QFN46_GL896-LQFN".$ C( ]2 t' S0 H8 A
#7 Warning [ALG0016] Part Name "TOSHIBA_TV00578002_0_FLASH_256_128_S71PL_N" is renamed to "TOSHIBA_TV00578002_0_FLASH_256_".% e5 s+ m! B% u% z3 ~
#8 Warning [ALG0016] Part Name "FAR_F5KA_897M50_D4DC_0_SAW_5P_FAR_F5KA_897M50_D4DC" is renamed to "FAR_F5KA_897M50_D4DC_0_SAW_5P_F".; p" V3 W/ t0 P
#9 Warning+ F9 A% e% Q$ _4 p: s( a
[ALG0016] Part Name "TCVCXO_1_CRYSTAL_3225_SQ3D02600B2JBA" is renamed to "TCVCXO_1_CRYSTAL_3225_SQ3D02600"./ i9 ]3 F  F; ~
#10 Warning [ALG0016] Part Name "BT_SAW_0_LFB182G455G9A293_LFB182G45SG9A293" is renamed to "BT_SAW_0_LFB182G455G9A293_LFB18".6 C) _5 S! I4 |4 v' |: j* y
#11 Warning [ALG0016] Part Name "SGM2022-EYN6/TR_SOT23-6_SGM2022-EYN6/TR" is renamed to "SGM2022-EYN6/TR_SOT23-6_SGM2022".
  L+ h5 l; z3 \& L#12 Warning [ALG0016] Part Name "SDFMM1N12CA2T_4_MT6188_MT6188(MTK)" is renamed to "SDFMM1N12CA2T_4_MT6188_MT6188(M".
9 e& ^8 Q4 N8 j& r#13 Warning [ALG0016] Part Name "CONN RCPT 14/SM_3_USB_12PIN_MUB01-AK22110" is renamed to "CONN RCPT 14/SM_3_USB_12PIN_MUB".
- M# N: e" g; K; B  s* L( l#14 Warning [ALG0016] Part Name "XTAL_3PIN_CARYSTAL_32K_32.768KHZ" is renamed to "XTAL_3PIN_CARYSTAL_32K_32.768KH".. z- \9 I' C  ^: m
#15 Warning [ALG0016] Part Name "4PIN_XTAL_CRYSTAL_3225_27MHZ/10PPM/7M32000035" is renamed to "4PIN_XTAL_CRYSTAL_3225_27MHZ/10".
/ D! b  G2 U2 S  Z#16 Warning [ALG0016] Part Name "BZX84C15/SOT_0_SOD2512_NC/CZRF52C6V2" is renamed to "BZX84C15/SOT_0_SOD2512_NC/CZRF5".
7 {+ v1 x0 ^  s6 X  DScanning netlist files ...
0 v: n' S) g- [# S# l1 x  ]% ^7 |
Loading... F:\PROJEC
" @! z2 H- r9 f' x3 aTS\CADENCE\G120\NETLIST/pstchip.dat
2 N0 A8 l9 t- i#34 WARNING(SPCODD-34): Expected ';' character on line 1078. Check the name and value syntax for invalid characters in the primitive definition before the line number.( {; Y+ R5 E/ Y  W7 }
              ERROR(SPCODD-47): File F:/PROJECTS/CADENCE/G120/NETLIST/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again.) \% x2 J' W0 w! T0 m
#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schematic and rerun packaging.
2 \/ M& o! j: V# i' l6 e! K#17 Error   [ALG0036] Unable to read logical netlist data.

/ G; B1 |. s3 n1 ?. r% CExiting... "C:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "f:\work\g-plus\g120\sch\g120_allegro.dsn" -n "F:\PROJECTS\CADENCE\G120\NETLIST" -c "C:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"& C/ i/ T! X- M! d9 o
6 J. K4 X; P) k; Q
*** Done ***- G" y8 p9 o% O' f. k1 x

3 F* R6 m& U/ D" c( M比如说:#1Warning [ALG0016]中的错误,我原理图中的Part Name 根本不是 "BATTERYCONNECTOR_3_KBC23S3M_R_BATTERY_CONNECTOR"如图1所示。字符总数根本没有超过32个,不知道这个Warning是什么意思!1 \' j  a+ N8 z0 J, f0 \

; ?6 h1 w7 E/ t  B其中网表也还有一些其他的错误!请各位帮忙解决一下!" N, X8 l3 y- A( r& K2 K; |
/ [& @+ X- d9 \' R+ q
谢谢!

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 楼主| 发表于 2009-8-23 09:35 | 只看该作者
本帖最后由 whb3103536 于 2009-8-23 14:10 编辑
/ _+ U8 T, s  B  }: u0 F* J
" W: N, Q* ~5 e- g还有一个问题想请教大家:" i- `7 R2 _) {
一般在用Capture CIS 转Allegro网表时大家用telesis.dll文件还是直接转成PCB EDITOR格式呢?哪种格式会好一些?9 c* h) q* H6 _7 x
1 h' [* a0 H+ b, l
我现在用telesis.dll格式转的话,就没有上面这个网表错误!
5 [) [/ L, {+ ~! T+ o请知道的朋友说一下!
! O2 Z" D/ t4 \谢谢!

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发表于 2009-8-24 22:48 | 只看该作者
关于那个警告问题,你可以不用关心,它是Orcad在转网表时的命名规则问题,命名时不只是原理图中的元件名,它还包括了封装的名称以及Value值,超过31个字符后,系统会自动截取31个字符,这不影响结果,可以不用关心

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发表于 2013-3-17 22:07 | 只看该作者
楼主 问下你的问题解决了吗?我遇到了和你一样的问题
- N/ N' ]. t/ F- v#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the design before packaging.4 o7 y& g1 F- l! }5 s$ U- q
咋么解决?
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