标题: 8片 DDR Layout Guidelines and Topology: [打印本页] 作者: tzwhzf 时间: 2009-8-1 13:54 标题: 8片 DDR Layout Guidelines and Topology: Layout Guidelines and Topology:* E/ ^5 t) G( T: F
The following are the routing guidelines followed for DDR memory interface section:5 H4 ?+ s. F- ~5 x0 S
1. Controlled impedance for single ended trace is Z0 = 60 ohm.- @+ V1 |. Y3 o* \( z) k8 j
2. DQ, strobe, and clock signals are referenced to VSS.2 g; ^8 L: W' _ y7 W0 _
3. Address, command, and control signals are referenced to VDD. ' [$ O) e; Y, P5 Q4. The length of address, command, and control signals are matched to clock with +/- 100 mil 9 o- V5 }9 ?3 J) R4 @( F( atolerance. . u* u) `4 b( U* q: B5. DQ <0..7> & DM signals are length matched with respect to DQS with +/- 100 mil tolerance & n( m( ?# \; G$ K5 ~5 [/ b4 T(byte lane). |$ e5 M7 @7 `
6. Each byte lanes are routed on same layer. b% u, c# X8 S" B- W7. Byte lane to byte lane is matched to clock with +/- 500 mils.. Z2 {: I6 w8 \
8. CK & CK# are matched with +/- 30 mil and are routed as diff pair with 120 ohm differential# N, {- r1 x. R8 E3 m
impedance. 9 x9 }. |! x& W9. Clock - pair to pair matching tolerance is +/- 30 mil. + c! h% L; z8 x10. Trace to trace spacing is 2X and signal group to group spacing is 3X. 9 P; ?" V1 o( s4 t11. DQS signals are routed in the middle of the byte lane (DQ<0..7>). ! j6 y# b2 r8 o12. Clock trace split point to DRAM is less than 1 inch.5 K- f7 |$ b9 a& }: w
13. VTT and VREF islands are separated with the minimum spacing of 150mils. 7 ^( ~) i. M4 ?1 x! p O14. VTT island width = 150 mil min.; 250 mil preferred.% G I$ Q$ Z* q$ J M q- g) Y. O2 v
15. VREF signal is routed with 20–25 mil minimum trace. 3 N( r$ [' f0 Y' J15. All signals are routed with minimum of 3X spacing between other signals ; M# |7 Q+ T/ J) P8 J16. Layer biasing is followed for dual strip layers.2 Y+ [7 E: ^2 F( \5 R0 D' Q6 U, d
Figure 1 shows the data bus topology and figure 2 shows the address/control bus topology.作者: tzwhzf 时间: 2009-8-1 13:58
元件放置方法： / P9 ]) K) l+ s' e
