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在PROTEL里画的PCB图转到ALLEGRO里面是出现的问题?

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发表于 2009-3-23 14:33 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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在PROTEL里画的PCB图转到ALLEGRO里面是出现如下问题Layout To PCBEditor   Version 15.7.0
2 R# X+ d; @  n$ D6 Y  }" n Copyright 1985-2006 Cadence Design Systems, Inc.
* i/ }5 H8 D9 s8 [WARNING (Layout To PCBEditor), Duplicate pin names were renamed in footprint 'BUTTON148'
, ?( F  n  N' z* I; a0 l( AWARNING (Layout To PCBEditor), Duplicate pin names were renamed in footprint 'TS5169'1 r' R/ O3 m; v% }  o; q7 @
WARNING (Layout To PCBEditor), Duplicate pin names were renamed in footprint 'BUTTON148_S1'
+ ~& R# P2 A& U8 i: Y, ~4 N$ IWARNING (Layout To PCBEditor), Duplicate pin names were renamed in footprint 'TS5169_U22'  f. {+ Z; c' p6 a4 t( X; ?
WARNING (Layout To PCBEditor), Netname 'SPI2_MOSI' was discarded because it is not used by any component pad( e5 j4 |8 n; L' K
WARNING (Layout To PCBEditor), Netname 'SPI1_MISO' was discarded because it is not used by any component pad
! X- m+ X: r% o3 [$ nWARNING (Layout To PCBEditor), Netname 'I2C1_SCL' was discarded because it is by any component pad
; ?. _9 S/ }0 f# D' R1 cWARNING (Layout To PCBEditor), Netname 'SPI1_NSS' was discarded because it is not used bynot used by any component pad
0 a8 w3 ]* o/ v, g; a2 b3 GWARNING (Layout To PCBEditor), Netname 'I2C1_SDA' was discarded because it is not used by any component pad8 x$ V/ x6 B6 }; ?8 R6 u
WARNING (Layout To PCBEditor), Netname 'I2C1_SMBAI' was discarded because it is not used by any component pad4 R3 z) q! h" w% i4 B$ s" m
WARNING (Layout To PCBEditor), Netname 'I2C2_SCL' was discarded because it is not used by any component pad
3 [, S% R  Z- y, KWARNING (Layout To PCBEditor), Netname 'I2C2_SDA' was discarded because it is not used  any component pad2 r( b7 R' Q1 ?) m" O: D9 O
WARNING (Layout To PCBEditor), Netname 'SPI2_NSS' was discarded because it is not used by any component pad
* c( u/ o$ v8 BWARNING (Layout To PCBEditor), Netname 'USART1_RX' was discarded because it is not used by any component pad# v  L6 D( w+ U* K  O. e) _
WARNING (Layout To PCBEditor), Netname 'USART1_TX' was discarded because it is not used by any component pad
! Q: I! J0 R: `' z% Z) A# ~ERROR (Layout To PCBEditor), Padstack '56' is malformed on layer 1
# d9 d# ~# B. K' {) W- w( Q" KNetlist Warnings and Errors recorded in 'E:\TEST\netin.log':% x. W" u+ Y% R0 \* i# |
/ G* p2 }- |, y) Y% x
Translate time 1 seconds
7 {$ F( Z0 X9 E& l2 [6 H& ?
, W9 D) L: E, J8 B3 w
# s% J* B& R' ^) n9 q( Z请高手解答一下是怎么回事呢?
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发表于 2009-3-23 22:03 | 只看该作者
估计是你的库和封装 没有导好..

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发表于 2009-3-23 22:08 | 只看该作者
Protel DXP在输出Capture DSN文件的时候,没有输出封装信息,在Capture中我们会看到所以元件的PCB Footprint属性都是空的。这就需要我们手工为元件添加封装信息,这也是整个转化过程中最耗时的工作。在添加封装信息时要注意保持与Protel PCB设计中的封装一致性,以及Cadence在封装命名上的限制。例如一个电阻,在Protel中的封装为AXIAL0.4,在后面介绍的封装库的转化中,将被修改为AXIAL04,这是由于Cadence不允许封装名中出现“.”;再比如DB9接插件的封装在Protel中为DB9RA/F,将会被改为DB9RAF。因此我们在Capture中给元件添加封装信息时,要考虑到这些命名的改变。
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