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标题: ee问题请教 [打印本页]
作者: rx_78gp02a    时间: 2009-3-18 21:15
标题: ee问题请教
把原理图转到expedition的时候有下列错误

QQ截图未命名.jpg (51.42 KB, 下载次数: 1)

QQ截图未命名.jpg
作者: rx_78gp02a    时间: 2009-3-18 21:16
点击那个黄色的按钮后出现：

QQ截图未命名2.jpg (18.68 KB, 下载次数: 1)

QQ截图未命名2.jpg
作者: rx_78gp02a    时间: 2009-3-18 21:17
Packager2 l5 b$ Z) y$ e  V
                                    --------$ ?" K  w% }/ `- j0 p0 P0 y

- v% N1 T& s6 Y" ?. f2 r8 e% Z                       09:11 PM Wednesday, March 18, 20091 r3 f) I) M* G% W) d4 C# h4 [
              Job Name: F:\新建文件夹 (2)\rfsdfdsfsf\rfsdfdsfsf.prj
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7 S% M. |  C0 p' L3 W  z     Packager     Version: 020806.00
+ v4 \; h; A" |. j. j% ?
4 x0 L* G9 @7 c9 B$ Q        Commandline is: "C:\MentorGraphics\2007EE\SDD_HOME\wg\win32\bin\Package.exe -j"F:\新建文件夹 (2)\rfsdfdsfsf\rfsdfdsfsf.prj"  -n"Design1" -Add "
/ O; P- [/ _( c/ |, a* N6 t% H- s9 w9 |4 S+ T
     The Common Database is at "F:\新建文件夹 (2)\rfsdfdsfsf\database".8 W4 |2 g5 b$ [6 Q" {5 i6 Z8 M  V

# w: g; N: ]9 ~. w7 Q     The Root of this design is "Schematic1".
" R, n6 k! P" C/ g: V6 p: ^2 W! U! ~' R( K- k3 u" A
     The Front End Snapshot of this design is "DxD".2 b0 }7 ?8 Y( j/ y3 q6 |

; ^* A7 X, D2 b6 W$ R2 Y6 Y     The PCB Design Path of this design is at "F:\新建文件夹 (2)\rfsdfdsfsf\PCB\Design1.pcb".
2 Y: L$ X( a# l# Q0 P9 P- ?+ F6 u3 n" l% b+ v( h( c
     The Central Library is at "F:\新建文件夹 (2)\EE2007_DX-Expedition.Central Library-o\EE2007_DX-Expedition.Central Library.lmc".& C! S/ K5 X# T! c( {

, `5 S( ]8 x' g+ @6 l     Unable to determine the Disable Repackage status.6 Y2 g( b- X. X4 F( J# c  {: z8 e) N
     !Repackaging will be allowed!/ L0 H6 |# Q; m" P

  ]- r0 N* x' v$ ~  s     The PDBs listed in the project file will be searched to satisfy the parts) |* P7 r1 L2 _: Y
      requirements of the iCDB only for parts not already found in the/ T% m# U0 M* V
      Target PDB., m1 `7 e0 l8 t5 d7 v

. m; M/ t/ k2 g5 t( e9 I     The AllowAlphaRefDes status indicates that reference- F  x3 @- Q: t7 _! m
      designators containing all alpha characters should be deleted
9 m2 r9 H% h" ]/ L' A) o; L# T! V      and the relevant symbols repackaged.  g$ h" ~# |, Z3 ]) |4 k
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     The cross mapping of symbol pin names to Part Number pin
# h3 w* t3 t2 v: U* j2 E; I' N% C      numbers will be checked for packaged symbols and mapped correctly
: s+ O6 y0 M$ r" e9 q; q' G' ?      for unpackaged symbols.! B: o! n/ S2 q, |3 k7 P

, O* U% o6 S3 Y$ S     Properties that have been checked off in the Property Definition Editor5 r; _( ~# v% [( g
      found at Library Manager/Common Properties will be checked for value
: \5 C3 y" N1 E# l* g      differences between the PartsDB and the non-null properties on symbols.; m" m4 @+ B$ U& ]
     Those properties checked off (other than Part Number)
+ K0 k" Q& a0 G. d, v9 ^      will not be transferred from the PartsDB to symbols.
1 C0 I6 ^$ `$ O5 d$ u     The following properties were checked off in the Property Definition Editor:
9 H$ I3 c! i; q' D9 a       "ICX_PART_MODEL"
2 c0 E: R2 K& v       "Spice Lib Name"
. ?; i4 H  ]* I  k; |       "Spice Subckt"
! S: M* Y* x  q( U7 H7 Z       "Spice Lib Path"
2 q: W  P4 R  z7 s' b4 _  R( M       "Use Verilog"
! G5 [" a' {6 B2 d+ a0 k) X7 q! Y: V       "Probe": X2 |9 h% _7 M% Y' y$ T
       "Prefix"' u" ~" d; R1 e7 o8 C( {
       "PARNAM"
) o1 o3 k1 ~! w/ o3 ]       "Order"# b4 d$ Y- h  Z! T$ t
       "No Pins"# c* i# ~/ e" e
       "Model"
7 g0 N" G# [" F7 z: W  @" J       "Load"  N, y( Z5 E+ O
       "LIBRARY"
( _3 N  Q- {$ s' t( C& _9 F0 J       "Generator"
0 D6 P8 [6 X; v+ y+ G: g! ]6 Q; z       "File"
/ v4 r% X- M4 s5 r3 }9 ?3 ~, k' L       "Bulk"
, O+ w! t% V/ B7 i; M5 }5 a       "ADMS Library"8 W, r& ]! N9 u! L6 ^
       "Parametric"' t0 {( h" K8 u9 s* @( [+ q
       "Value2"3 T6 c8 `& ~# w- j7 c
       "Tech"
2 E1 E6 t% l( {" k       "IBIS"4 F; Y; a4 g3 X: d4 o/ `
       "VHDL Model"9 T2 H0 k/ I6 z% }
       "Verilog Model"
, a8 `. @( a5 M( E/ |       "Simulation Model"
, [/ f: l, D7 W, p& `       "Value"
4 X2 F% O0 d8 M6 F8 x6 ?# r. t8 Z! e3 L  g2 n& w; G, S1 w1 i, Z

' m; q8 V; d# I0 h/ Z7 l; A8 O; ?2 m5 k! m( @3 T$ B
     Common Data Base has been read
5 R1 o! X' |2 i, {; c: A4 c
5 u+ J1 d4 s2 B2 ?2 N7 R% }     Target PDB Name: Integration\LocalPartsDB.pdb9 ]  {$ H/ z0 e( K% B; D0 r

9 {, w; f: E3 [4 v; Q0 ]! ]( h+ ?0 Y; R     ERROR:  Unable to open Source Parts Data Base F:\新建文件夹 (2)\EE2007_DX-Expedition.Central Library-o\PartsDBLibs\Module-Through.pdb for reading.4 L# Z" u2 H) N" Q5 Y3 W
      Suspending getting parts by Part Number.
8 G- V, f7 b* D- s3 T6 U0 h9 e' n7 M) Y6 Y" o" D4 l! ^
     ERROR:  Unable to create local PDB
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- b# l( ~8 A3 B9 x     ERROR:  Problem Making Local Parts DataBase1 V  e. M, X. }3 I, g$ n+ F, I
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8 P! u1 E' z5 _  `9 W! E- r3 l     Testing of Packaging is being terminated with 3 errors and 0 warnings.
3 m" M" C, ?( o$ K( ^0 A3 c      Design has NOT been packaged.& t- z# ^& {# e$ i

% v- j2 J8 S2 _5 r6 i     There have been 3 errors.
作者: qisaiman    时间: 2009-3-19 18:36
pdb中元件没找到导致的吧，是不是cdb流程 没有生成parts？
作者: rx_78gp02a    时间: 2009-3-20 19:31
有parts，是cdb流程！
作者: liuli    时间: 2009-3-20 23:20
路径中不能包含中文吧
作者: rx_78gp02a    时间: 2009-3-21 16:56
包含中文路径的话symbol editer不能用！但是原有的part什么的可以用，只是symbol不能修改而已
作者: finezhang    时间: 2011-11-12 16:45
版主，遇到你2年前的问题，怎么解决？能不能给个简单的工程，哪怕是一个元件都行，主要学习一下流程，怎样从原理图到PCB
作者: rx_78gp02a    时间: 2011-11-12 22:01
finezhang 发表于 2011-11-12 16:45 & W8 b& P, y  @% o5 n9 d
版主，遇到你2年前的问题，怎么解决？能不能给个简单的工程，哪怕是一个元件都行，主要学习一下流程，怎样从 ...

7 }; P, w, ]/ {6 z2 g{:soso_e153:} 两年前的东西不知道当时是什么原因了！{:soso_e141:}
作者: ksk115555    时间: 2011-12-7 16:56
哎，一样 最近遇到此问题，我是库定义的时候，没有在SYM中定义PART NUMBER，搞了半天



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