标题: C@dence.SPB16.20.winnt.Hotfix.001和002所更新的内容 [打印本页] 作者: zlei 时间: 2009-2-11 23:03 标题: C@dence.SPB16.20.winnt.Hotfix.001和002所更新的内容 HOTFIX VERSION: 0023 C8 F! I4 G. W A; D
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======================================================================================================== 2 f6 j( F% A0 q7 U) I511865 SPECCTRA REGIONS Diff pairs should adhere to constraint area 9 v7 Y. R5 W5 |; E564589 ALLEGRO_EDITOR OTHER The show measure command should show the actually measured po ! q5 X: i! u, V3 J- L+ S i9 N9 e: ?570861 CONCEPT_HDL CORE Unconnected mark does not be removed even after wire is conne 2 x# Y2 C% v" H$ T/ ~1 ^. c572188 APD PAKSI_E 3-D model extract failed# l3 o8 t6 l, w& |# u
578164 CONCEPT_HDL SKILL Cnskill crash during Create Test Schematic step when large pi! P. P2 L8 d+ w2 A& \& [
578874 SIP_LAYOUT DIE_STACK_EDITOR Stackup editor in SiP fails to add layers above and below top3 V. `& c% p7 D5 o% s
580315 APD ETCH_BACK Etchback trace fails with error "W- An etch-back trace cannot ; D/ Z7 m$ i7 l4 r582308 ALLEGRO_EDITOR OTHER Create Detail for bondpads rotated at (0,90,180 and 270) angl ) t5 ]# |7 j+ Z- L- h; U9 j8 f594370 SIG_INTEGRITY OTHER Wrong description in case update form when changing preferenc# C2 R0 j% t# g) L# I: u9 Z
595755 CONCEPT_HDL CORE Rumtime error happen when do Move Group in conceptHDL' w9 Q0 @8 L* @ ^" U/ V; n
597922 SIG_INTEGRITY TRANSLATOR spc2spc doesn not handle inline RLGC DATAPOINTS% c+ T2 i' x" `9 M) m1 d4 u& g% m K7 B
606620 ASSURA DRC Problem with density checks in Assura9 S: T, z# n. u8 J
609866 SCM SCHGEN Schgen replaces CTAP with COMMENT symbol which causes net sho % L4 F1 t( m! h7 a1 e2 a611678 ALLEGRO_EDITOR GRAPHICS During Place > Manual Pins disapear if component is on bottom - ^2 r. g8 b, X- F3 W615630 ALLEGRO_EDITOR GRAPHICS Pins are not visible when place manually is used for Bottom s ; p- J' ^3 s* t- {& r) q3 C/ O* z( N615764 CONSTRAINT_MGR TDD BOM report does not filter parts with BOM_IGNORE + r& _& Q; Q# T3 P, d5 J616529 CONCEPT_HDL CORE 15.7 Design Entry HDL fails with Out of Memory message $ O2 F( A; N+ C: ~" U616928 CONCEPT_HDL CONSTRAINT_MGR Net_physical_type and net_spacing _type constraints not sync'( r1 z" o* j" u* a! k
617441 SIG_INTEGRITY FIELD_SOLVERS Reflection simulation fails when using wideband vias 7 F- w0 U& w7 t9 A X6 b617679 ALLEGRO_EDITOR COLOR The color palette will not be saved with the design unless co3 g8 w( f# N3 U$ s( ~+ ]! j0 D
617805 CIS PART_MANAGER Capture_crash : D4 e- ?4 l% X618988 ALLEGRO_EDITOR SCHEM_FTB Long bus names being truncated % E& _8 c/ q4 w9 }* e619588 APD EDIT_ETCH Poor routing performance. 5 second delay after each mouse cli . J# N" V; l5 ]619691 SIG_INTEGRITY FIELD_SOLVERS Problem of EMS2D by using FreqDepFile. l8 c3 X9 M/ l4 G4 r. |
619867 ALLEGRO_EDITOR DFA DFA_BOUND_TOP shape doesn't display DFA Audit conflicts # Z, i* }- c. W, t+ }$ ~8 v( k620359 CONSTRAINT_MGR CONCEPT_HDL ECSet and Netclass definitions lost in the FTB process : D4 `5 u! F+ y620424 CONCEPT_HDL CONSTRAINT_MGR CM restore from definition of subblock removes ECSets defined ' k6 Q: D# g$ @, C" w+ h620700 ALLEGRO_EDITOR PAD_EDITOR Shape has bigger void on Y direction for Oblong SMD Pads% B3 ?" u! |, f8 d
620868 SIG_INTEGRITY PAKSI_E Wirebond material conductivity is not used by PakSI, only a d 5 s* c) a% p+ `$ c4 }( ^6 H+ E620895 ALLEGRO_EDITOR DRC_CONSTR About error message of cns_design command. % Y7 h1 P) E5 w0 x9 p U$ y; T620924 CONCEPT_HDL OTHER PDF Publisher 16.1/16.2 can not output some Japanese characte 2 ^) H* V% X8 G& H: m621156 SIP_LAYOUT ASSY_RULE_CHECK ADRC Rule for 揟race Minimum Angle to Pad?not showing all th5 [" k/ V: i5 r2 `& k, u- y5 ?4 r
621163 SIP_LAYOUT ASSY_RULE_CHECK Ambiguity about the how is the 搒tart of the wire" defined in+ @2 [1 o/ n \% P& o' |6 x
621298 CONSTRAINT_MGR UI_FORMS PCB SI crashes when importing a constraint file into Constrai8 {8 {( s# x3 v5 }1 N. z; g
621315 ALLEGRO_EDITOR PLACEMENT Getting wrong component when using Place replicate unmatched 3 m& a5 S7 m7 |* h, `* s. n621848 CONSTRAINT_MGR TECHFILE techfile write fails with Failed writing object attributes, E$ q8 O0 T7 H, f* p- W6 N
621867 ALLEGRO_EDITOR TESTPREP Transcript window randomly locks up when running TestPrep+ E3 y% W* b. i5 ^: y0 `" F2 O
621901 SIG_INTEGRITY OTHER Incorrect extracted via drill/pad diameters and missing inter' A, A5 A7 D; h; u/ K
622010 ALLEGRO_EDITOR DATABASE Undesired openings in Negative shape 8 I3 `) d; Z% O1 q U! r J `5 Z622062 CONSTRAINT_MGR DATABASE Importing dcf file at system level crashing the Allegro PCB e 1 q. b$ v' x) L% l& s0 R622156 ALLEGRO_EDITOR SHAPE Thermal/Anti value producing incorrect void sizes2 Q# ^4 {4 r4 n- y4 \) B6 U9 `% Z _
622450 SIG_INTEGRITY SIMULATION Field solution failed/ h) K+ h3 K0 }" u* m5 y
622466 ALLEGRO_EDITOR COLOR layer priority in 16.2 0 k6 i+ q9 ?# L9 C622566 ALLEGRO_EDITOR SCHEM_FTB Replacing the components of same refdes on board after import' U( c3 x0 d& ]) r* ?: k {! x
622700 APD PLATING_BAR Plating Bar Check is highlighting Nets that appear to be conn7 ]( t {$ i' `
622862 ALLEGRO_EDITOR ARTWORK Allegro crashes when we enter a value in the field file size: H0 q g- q) N
622989 SIP_LAYOUT IMPORT_DATA Type of Wirebond die changed after die import* ]$ M6 Z+ H$ R* |# i
623182 SIG_INTEGRITY FIELD_SOLVERS Extract topology crashed % U/ @ ]. `% o7 Y623300 SIP_LAYOUT 3D_VIEWER Wrong placement of Solder Mask Bottom in 3D view file% E! h$ b" b7 \. b9 L' J
623384 ALLEGRO_EDITOR VALOR Valor output showing padstacks on 45 degree angle wrong in 168 r% c+ k) F. X. F0 U" w3 v% x
623489 ALLEGRO_EDITOR EXTRACT Allegro tools Report etch length by pin pair takes forever to * J* n' `2 [0 H4 k# C! v( x5 g1 x623529 ALLEGRO_EDITOR EDIT_ETCH Manual tandem diff pair routing has been lost in the 16.2 rel ' g* [$ V8 Y/ |* d* ?& X. L; R623536 F2B PACKAGERXL packager fails with memory allocation error . w# j! r! d/ x9 i. t0 t. h" Y/ n4 ]623673 CAPTURE OTHER Unable to get capture window size to full-screen in dual disp ! }; w2 x6 K# h623701 ALLEGRO_EDITOR OTHER 'Analyze' menu missing when opening Allegro PCB Editor L - Pe / z% h# H# N* g* u1 R623738 CAPTURE PART_EDITOR Create part from spreadsheet is not working correctly' o7 z. T8 k2 ^
623740 ALLEGRO_EDITOR OTHER Can we use variant.lst file as list file in find filter- v! [+ O8 Q1 I4 x9 E: t, _, [
623745 CAPTURE OTHER Capture crashes when the user tries to place markers' ~5 H+ [, x: b& q; @1 X# k& I+ R% D
623813 SIP_LAYOUT WIREBOND Add wirerbond only is not working in this case with a bondfin ! A* A& |2 V, U. M623830 ALLEGRO_EDITOR MANUFACT backdrilling is drilling through component pads on the bottom " e0 A$ F5 w6 u6 v9 H' j624048 ALLEGRO_EDITOR OTHER Viewlog for Export to 16.01 is not closing from any of the 'C5 |) x- G! V0 [( u K" n
624223 ALLEGRO_EDITOR GRAPHICS disable_datatips variable is busted 7 C: {, U q; i! j( Q# {624495 ALLEGRO_EDITOR SHAPE Static shape did not void to drill holes z2 J8 Z. m1 J F624599 SPECCTRA ROUTE PCB Router hangs on route of design / v% S% R" @$ f2 I& j6 t! ]5 u/ Y624653 APD BGA_GENERATOR BGA Generator fails at 400um pitch % H# U1 O, V% O5 C/ |- ^4 z624812 CONSTRAINT_MGR ANALYSIS Importing dcf at the system level causes RPD constraints not 1 g" x* z) y! ~5 T624888 ALLEGRO_EDITOR DRC_CONSTR Regions and RCI's Cset not working as expected* M( @' F7 U" S
624958 ALLEGRO_EDITOR EDIT_ETCH Slide in region is changing etch to min line width ' i: C! M8 S+ N* r8 j- }! }625251 ALLEGRO_EDITOR COLOR 16.2 Linux allegro - new subclass created does not reflect in& W$ Z3 Z+ k( [
625273 APD IMPORT_DATA Import a .mcm into SIP in order to edit the die pins. Edit -> 3 |/ x1 Z: W# \# Q625279 APD DIE_EDITOR die text in fails when the function name is >31 characters wi + t; }0 }) I* {; g. W& L2 H# L5 L4 |625304 SIG_INTEGRITY IRDROP Need a better understanding of absolute current values report - j2 K8 {7 c/ O2 I, w625367 ALLEGRO_EDITOR DRC_CONSTR drc_fillet_samenet does not work correctly 0 G; f$ s+ I; K1 H625551 ALLEGRO_EDITOR SHAPE Dynamic shape is not voiding to route keepout correctly * l( G' \) I$ C d/ H: i625852 ALLEGRO_EDITOR DRC_CONSTR Some buses in CM are disappeared after import CIS 3 .dat netl% T/ h& {- j- F9 g4 g6 ]
625885 CAPTURE DRC Report misleading Tap connections check for DRC reports error : d8 W- Z) a9 W# z- j625972 CONSTRAINT_MGR TECHFILE techfile import fails with Failed writing object attributes6 S. {: E. I3 M9 u1 g. v
626630 CAPTURE NETLIST_ALLEGRO Capture 16.20 hangs endlessly but Capture 16.0 prompts result& h0 z( Q4 }$ M7 P4 q4 F F6 [) R
626669 SIP_LAYOUT OTHER 16.2 radial router find filter does not have option for bond e/ @# f6 B2 { B8 G0 B
626671 SCM OTHER Adding signals in ASA is taking too long7 K4 C d$ l1 ^) v& M; y( [
627228 ALLEGRO_EDITOR MANUFACT Dynamic Fillet is disappered, when use slide command.1 R9 W: b0 x8 d6 \. }
627289 SIP_LAYOUT DIE_GENERATOR Pins connect at the same net name after Die Text In8 h& w0 c9 K, ]+ t' l: T
627864 CONCEPT_HDL EDIF300 EDIF c2esch crashes, w$ z2 i+ N/ h
628169 ALLEGRO_EDITOR OTHER write command changes design name in constraint manager $ @/ W8 p# {9 o X1 t628220 SIG_INTEGRITY SIMULATION Reflection simulation failed with filed solver "EMS2D" # k0 {4 b5 }+ H# _. p3 k628261 APD OTHER no "Tangent Via Line Fattening" in APD products " l% O% u1 ?# e: L; Z% b$ I. u! D628922 APD REPORTS Metal Area Report shows 0.00 on one layer X" g& U/ v g; T, k& f( {HOTFIX VERSION: 001 " Y# N, k% j5 E5 F7 o========================================================================================================9 L s/ g% L7 F! K- |6 o
CCRID PRODUCT PRODUCTLEVEL2 TITLE # y3 q/ L @) f4 A======================================================================================================== " ]6 B+ F h8 G6 F191020 ALLEGRO_EDITOR SHAPE Shape edits results in same net DRC being reported.% z' V; L3 x6 ]
230469 ALLEGRO_EDITOR SHAPE Allegro improve performance of Dynamic Shapes, @5 {& H3 @, M- C x1 G
295039 ALLEGRO_EDITOR DFA Allegro DFA to be enhanced to include height; S8 m2 y; v! Y# Z+ \# k0 v
346863 CIS DESIGN_VARIANT Variant View mode is not working for multi-section parts 4 J e# a) L v( j6 c q6 i0 P9 i400036 CONCEPT_HDL HPF nihongo_vector_font should be listed in the Plot Setup GUI1 V* y! ]0 ?- x% p5 d( ^: H
410092 CONCEPT_HDL OTHER The Imported sheets loses the write permission for the group * N( b) e; N# l m) w& I415462 CONCEPT_HDL MARKERS The SPB157 Markers does not normally display the Japanese fon7 E- t; ?+ L! O9 `! H: b J1 F
501802 ALLEGRO_EDITOR GRAPHICS When hilighting parts or nets the system is inconsistent on z/ f8 M, S9 ~8 l/ `) u
503526 SPIF OTHER SPIF is NOT defining class for class to class rules.2 }& o3 C7 _" P& r3 j
511175 CONCEPT_HDL CORE Copy All causes - No object selected error7 P0 y8 _! W& P9 _2 m' d/ o
526774 LIBRARY DEVELOPER Pin抯 text size goes back to default size after change pin na 4 Z& }. Z2 G& a- ~533536 CONCEPT_HDL OTHER The font used in published PDF is not identical. % m. @. s8 S) r; R; H* Y537769 CONCEPT_HDL CORE Sporadic behavior of DE HDL toolbars for adding components ge9 L* {" H: F* L
544519 ALLEGRO_EDITOR MENTOR mbs2lib Generating extra "b" version of footprint during tran 5 U1 @$ ^# H/ Q8 q" o$ r551528 LAYOUT OTHER Layout2Allegro L2A translator not translating reference desig ! O! J) y; P4 `6 z551614 SIG_INTEGRITY IRDROP Import and export of IR-Drop setup ' X# g; Q! |$ [- F* a8 a4 l7 G552127 LIBRARY LIBUTIL When -lib is missing from con2con PTF files get re-written in# s1 u; q$ L% A
560417 ALLEGRO_EDITOR OTHER Part Logic does not read part row from ptf file and assign in, P5 n& N D+ g# U/ H+ l" d
564954 CONCEPT_HDL CREFER Crefer attaches $XR property to other $XR on RHEL. + C+ N4 K1 D& K6 f' Q, X: k3 m565798 CIS DESIGN_VARIANT all the sections of mult part package are not coming as DNS i* q" B% i- y6 P6 V& o
571627 CONCEPT_HDL CONSTRAINT_MGR cmuprev fails to synchronize constraints on low assertion vec 6 v$ a* a/ }+ c- @, K2 e' ^, i577915 CONCEPT_HDL ARCHIVER zero folder is not archived how the archiver is working ? , i! D) ~2 v; T8 n: p! M- Q581446 LAYOUT TRANSLATION L2A fails with pin numbers do not match between symbols from - y" F$ E( E' A6 ]* k. n3 p583891 ALLEGRO_EDITOR MENTOR Mbs2brd will not run with PA5630 license (Allegro PCB SI GXL) 5 t. m% i+ y# a% Z. Y. @- g. [) Z586998 ALLEGRO_EDITOR PLOTTING Board shifts towards top left when plotting at higher resolut1 M! K2 r5 d1 f1 @) t
587870 ALLEGRO_EDITOR PCAD_IN Import PCAD fails due to dupliate pad name. Caused by a peri , S% t9 k; L5 d6 `+ l; P+ R4 A588949 CONCEPT_HDL CORE Importing schematic pages from another project crashes Concep2 S7 Z0 W5 E: n% \
592340 ALLEGRO_EDITOR MENTOR MBS2LIB not creating the correct shape in symbol# G8 O) \3 h: w! i, D' y6 X
596530 ALLEGRO_EDITOR PADS_IN PADS to Allegro Translator removing/renaming reference design. M3 q: m' x! F2 ]
596638 ALLEGRO_EDITOR EDIT_ETCH The timing meter indicates untruthful violation" Q" r+ Z1 ]; H7 M5 N0 [! |
596716 PSPICE DEHDL Flag error due to part pin mismatch while create netlist 5 t5 S; ?. X' [8 @( _4 o8 e) Z3 J597685 ALLEGRO_EDITOR SCHEM_FTB ratnest are out of date error in DBDoctor after import logic, ]0 @: V3 H9 L$ N* }4 e
597937 ALLEGRO_EDITOR PADS_IN Request PADs_in to translate keepout areas 6 Q' ^: P9 k" @- f# U0 m$ ]# a598575 ALLEGRO_EDITOR OTHER During Split plane should it use settings regarding fill styl ( O6 g+ F! a5 q+ m: p598814 APD WIREBOND bondfinger does not move relative to its origin using ipick 2 e( b5 v9 O& Y( b8 i1 o599823 CONCEPT_HDL CONSTRAINT_MGR Lost ref to dml-lib causes loss of cm data even if the refere$ \( I0 @. c* M: d
599886 APD EXPORT_DATA bodygen batch tool is failing to generate .css file 7 G4 c# k; B# U3 |! p8 n, c, o603425 SPECCTRA PARSER Do file fails Syntax error in command unexpected end-of-line 2 W6 Y% f/ Q6 O1 G/ _! r: J7 w603987 APD OTHER Offset via generator should ensure pitch distance is met or e # H8 W& B# @( o% B% m1 N604377 SCM PACKAGER Output board name containing a dash causes scm crash M- h+ ^' X; N( D& c% T# x
604614 CONSTRAINT_MGR OTHER netrev is unable to update the Canonical paths with the new d 6 Y _9 E+ ^* }9 ]6 {604794 ALLEGRO_EDITOR PAD_EDITOR Replace Padstack reports error pad missing not true.8 `( s: O3 j' R. i( z) s
605169 ALLEGRO_EDITOR OTHER Can design_compare handle swappable pins?0 Z3 P* K2 K0 Z, r# s
606586 ALLEGRO_EDITOR INTERFACES Multiple drill in padstack cannot be shown in Pro/E IDF. E/ L0 r1 t1 S
607217 APD IO_PLANNER wirebond die replacement from IOP 9 q/ W0 O4 n; u4 n& I+ s1 {9 V/ \9 g607222 APD WIREBOND auto wirebonding creates wirebond with DRC' i) S& @1 C/ J/ v [9 P& Y
607644 ALLEGRO_EDITOR MANUFACT Enhancement to increase the IDF export ''default package heig- y2 |& J3 L( s+ e6 Y' B
607718 CONCEPT_HDL HDLDIRECT HDL Direct Errors reported while generating simulation netlis4 o5 x0 X2 }+ Y- n7 r! R9 A
608233 SIG_INTEGRITY FIELD_SOLVERS Convergence errors with analytical vias when drill size is 1 2 e2 f5 f9 }' i; s8 [& S609549 ALLEGRO_EDITOR INTERACTIV Mirror Geometry command to change BB Via's layer." A- J; g: D! X. o7 \) R
610028 SIP_LAYOUT IMPORT_DATA De assign NC nets during aif import : c+ l, L; D( J" z# M" P% G610134 CONSTRAINT_MGR INTERACTIV Cross-probing from CM to Allegro no longer works on system le * G& i; p* L- @4 }8 G" F610276 ALLEGRO_EDITOR PADS_IN PADS to Allegro translation is failing with error." S+ \8 J6 X" N* b( N; ?& J: `5 W
610482 ALLEGRO_EDITOR SCHEM_FTB Netlist swapped net names on 2 pins causing shape to lose its6 l. H. t% M) Q2 s, {1 B" ^
610681 CONSTRAINT_MGR DATABASE An exported constraint file can not be re-imported in V16.017 j! N/ o+ `3 T9 B1 x! [7 [7 f
611260 ALLEGRO_EDITOR DRC_CONSTR Routing a diff pair it does not follow Physical line width se + b* ?+ ]7 Y! }( q8 w611425 ALLEGRO_EDITOR MENTOR mbs2brd crashes when importing Mentor ! [: _( h6 n( [4 ?3 d* b611697 SIP_FLOW SIP_LAYOUT octagonal bumps have offset in SIP compared to the chip view* v6 W: _& b3 r* B9 J9 V
611807 APD WIREBOND Duplicate paths created on wirebond import for some cases.0 _" Q: |' k( [: y* q9 ^' B
611856 CONCEPT_HDL GLOBALCHANGE Ref des deletions after runnning Global Change to change $LOC % k* R1 x& Y& z611874 CONCEPT_HDL OTHER Crossprobing one symbol in Concept using Occurence edit mode$ k9 O; o6 V' B" U
612088 PSPICE DEHDL_NETLISTER Fail to create the netlist for G value expression* y# t/ @6 C$ \0 |& L/ Y
612195 ALLEGRO_EDITOR DATABASE Adding layers to the default cross section causes phantom tex 4 R- v1 J+ ^' \9 i7 z6 a [( w& p0 i7 z612237 ALLEGRO_EDITOR SKILL axlFormColorize does not change the full background area of a ' E. C. W+ V2 S7 L612299 APD DEGASSING Degassing static shape creates voids inside of voided areas , }6 E9 R) b$ S- s: {3 g612560 CONSTRAINT_MGR OTHER Diffpairs don't show the CSet assigned through Net Class ; @! V. z* e# f2 {612587 APD WIREBOND Unchecked Allow DRC option creating disconnected wire bond. $ \% G# F0 b( Y3 f! A612884 SIG_INTEGRITY SIMULATION When using ViaModel $ [) C# S! a2 _; S h/ \0 `) E, M; a I612914 ALLEGRO_EDITOR EDIT_ETCH Centered via option in fanout command not available when swit8 i& J" ]" a* F3 I, K6 ]! I
612939 SIP_LAYOUT ASSY_RULE_CHECK ADRC Continuous Solder Mask check problem0 d) i3 M* c; ]" z* d; W+ \- i9 f
613553 CONCEPT_HDL EDIF300 edif schematic writer crash on this design ) p3 S& f% E3 Q5 `613565 ALLEGRO_EDITOR EDIT_ETCH Allegro Editor Differential Pairs are routing incorrectly : l0 R6 f3 m7 |, P2 M. R7 \613736 SPIF OTHER Spif fails to write class data8 ?4 s1 B$ U8 G3 C; Y* }1 ^
613990 POWER_INTEGRIT INTERACTIV PI is crashing during capacitor selection8 H3 P. o" C7 E, {& q
614278 CONCEPT_HDL EDIF300 pin text note and flag are not visible on reloaded edif file- [# o$ H7 l& \3 O5 p/ K
614371 SIP_LAYOUT WIREBOND Any wirebond command crashes the application9 i) Y9 I1 `: _# s$ A
614407 POWER_INTEGRIT INTERACTIV PI crashes when editing capacitors5 T4 N6 R8 `" H. N7 _7 r8 W- G9 c
614727 SPECCTRA GUI Allegro PCB Router can not process the dsn and rules file for: L% Y2 D* ?( l( U" \7 S. T
614972 ALLEGRO_EDITOR SKILL axlCNSSetSpacing does not change the value of the "testvia to " O! K8 b4 n$ Y# }% w615144 SIP_LAYOUT 3D_VIEWER die placement does not change with changing in soldermask thi, K8 m: t* N( ]& `
615431 LAYOUT TRANSLATORS padstack names are crippled or renamed if it has over 18 Char# T: d2 _7 Y. r% z3 [* S
615506 APD MANUFACTURING Sort by die pin location for Manufacture Doc Bond finger brok" C( W9 r( O9 [; \" p
615745 SIP_LAYOUT DATABASE Move die symbol with stretch etch on is disconnecting wires f 3 S- }2 u" _& A! ]9 l1 k5 F615816 SPIF OTHER Allegro match group members not translating to PCB Router; mi ; _% c& q2 C* I) z616104 CONSTRAINT_MGR OTHER allegroTechnologyFile XML format issue( _% t, k7 K8 f9 u/ k7 A7 R; p: F
616122 LAYOUT TRANSLATORS Protel to MAX translator problem with package outlines and re) b' H0 Z( J8 h7 B3 r5 p9 S
616404 ALLEGRO_EDITOR OTHER Design compare fails with message "Invalid input argument" wh' V" u9 w/ Y$ L) w
616713 CIS PLACE_DATABASE_PAR property name with "&" charecter in access database causing c: T, J, ?0 z# w
616818 SCM PACKAGER BOMHDL -type scm fails on schematic block" W+ j& |% S: _( @( p0 t+ f
616907 SCM VERILOG_IMPORT scm crash during Get Module Name8 w: ?" M/ o* }" V$ g9 ]
617058 APD WIREBOND wirebond space evenly does not work for fingers on power ring6 p; {& N; O/ @6 r* O' E: w, d
617083 ALLEGRO_EDITOR INTERACTIV Windows tabs hangs on Linux l5 d8 Q: a% \2 j
617236 ALLEGRO_EDITOR SHAPE Editing a shape in a void causes the bigger shape to drop seg $ t1 u5 D# ]* h! J617351 CIS DBC_CFG_WIZARD XML writer fails if DBC location doesnt have write permission 9 o: f$ |* M& {! c617515 SIP_LAYOUT OTHER Be able to invoke Velocity from cdnsip* s" f/ N! w8 E" S3 x8 o2 U8 e
617761 LAYOUT TRANSLATORS Value property for Library symbol of Orcad Layout is not tran * u. C! Q$ Q7 v, k6 a8 W0 I617890 SIP_LAYOUT WIREBOND Push and shove on Bond fingers with multiple bond wires cause* f6 I8 C$ i, Q' {" y: y
618184 APD OTHER database diary on unix/linux 9 X6 o# O- g" |: y1 {4 i4 ~. z, n; B618201 ALLEGRO_EDITOR OTHER Dynamic fillets take a long time to complete 9 _9 |, u0 e, i/ A: E618545 ALLEGRO_EDITOR INTERACTIV Allegro crashes when we place a package symbol for Jumper usi & b W( U9 l e" P# o618610 ALLEGRO_EDITOR MANUFACT Delete a cline seg creates a fillet5 H b4 ~4 j9 p6 T8 d
618651 SIP_LAYOUT IO_PLANNER Bondfingers and die are shifted every time an update package / \- n! @- Y: O/ P618712 ALLEGRO_EDITOR EDIT_ETCH Shove mode is not working on Diff pairs in PCB Design L 6 l; Y0 m$ G- Y$ q( W0 Q' n618836 ALLEGRO_EDITOR SCRIPTS Allegro does not interpret recorded macro script files proper : P. F) _7 u+ [$ g) s) [1 ] w618946 ALLEGRO_EDITOR INTERACTIV Allegro crashes while using Place Manual -H 8 ?1 c' o! h( H618984 ALLEGRO_EDITOR COLOR Layers on Allegro Canvas does not match Color Dialog Box 1 l- ]0 T9 c3 q0 ]619007 ALLEGRO_EDITOR SKILL Skill command does not accept spaces in file path/name 6 [8 A) v3 C, F. _619033 F2B PACKAGERXL Pinswap lost on backannotation5 ?; }% n2 u' t2 O
619268 POWER_INTEGRIT SIMULATION IR-Drop can't sees via on pad as open }; d+ {0 `+ A6 u7 f) ~
619356 CIS FOOTPRINT_VIEW Footprint preview only from 1 directory in Capture.INI1 v( d) G2 `! W" W- H* y
619712 ALLEGRO_EDITOR EDIT_ETCH Unable to route in the Bubble Mode for Partitioned board % q5 P' I" C3 ^1 `9 n+ [619773 ALLEGRO_EDITOR DATABASE Uprev for 13.6 and 14.0 files not working with SPB 16.2 on Wi( `" s& G$ r' i7 J- l4 S9 i8 p
620064 CONCEPT_HDL CONSTRAINT_MGR Loosing Diff pair constraints from lower blocks when packagin % d6 C- T( \+ w8 m. J/ z622132 CAPTURE NETLIST_ALLEGRO Incorrect ALG0078 error for complex hierarchical design