标题: Synthesiable High Performance SDRAM Contoller [打印本页] 作者: Haiting32451 时间: 2016-6-12 10:59 标题: Synthesiable High Performance SDRAM Contoller Synthesiable High Performance SDRAM Contoller
Synthesiable High Performance SDRAM Contoller
Synchronous DRAMs are available in speed grades above 100 MHz using LVTTL I/Os. The
Virtex? series of FPGAs and the Spartan?-II family of FPGAs have many features, such as
SelectI/O? resource and the Clock Delay Lock Loop, that make it easy to interface to high
speed Synchronous DRAMs. This application note describes the design and implementation of
a synthesizable, parameterizable, flexible, auto-placed-and-routed synchronous DRAM
controller in the Virtex FPGA family. The design can also be implemented with a Spartan-II
device. A 32-bit wide data interface version can run up to 125 MHz when automatically placed
and routed in a Virtex -6 speed grade device. Hand placed versions of the design can run even
faster.
