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Care should be taken with the physical layout on power and grounding of the TSC circuitry. : E; x- {6 x/ _* J3 p) y0 }) T3 w4 m! }, ^4 y
The analog-to-digital converter (ADC) in a TI TSC device is a successive-approximation-register (AR) architecture ADC. The generic SAR architecture is sensitive to glitches or sudden changes in the power supply, ground connections, and digital inputs that occur before latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. Once the SAR ADC has made a decision to keep or reject a bit-value, the converter cannot go back in time and change the previous decision. + o2 |7 }- }' }1 m # e! u* Z& O# D" w* x L( zWith this consideration in mind, power to the TSC device should be clean and well-bypassed, with bypass capacitors between power and ground. A 0.1μF ceramic bypass capacitor should be added between every TSC power supply pin (which could be named differently with different devices in Table 1, such as +VCC or VDD or VREF or IOVDD) and corresponding ground. A 1μF to 10μF capacitor may also be needed if the impedance of the connection between the TSC’s power supply pin and the power supply is high. These bypass capacitors must be placed as close as possible to the TSC’s power supply pin, optimally right up against the TSC. From the ESD protection point of view, the traces connecting the TSC power supply pin’s bypass capacitors to ground should be as short as possible. The TSC side of the capacitors needs to be placed right on the +VCC/VDD/VREF/IOVDD trace and the other side of the capacitors right on the ground plane. Using flow-through design instead of T-shape connection is recommended for decoupling capacitors to minimize parasitic inductance associated with the connections between capacitors and power supply line. ( q% P# _/ I$ s, o- x2 S8 l# d) k4 j- z" J3 m$ V5 Q
The ground pins of the TSC device and its analog surrounding circuit should be connected to a clean ground point. In many cases, this point is the analog ground. Avoid connections that are near the grounding point of a microcontroller or digital signal processor. If needed, it is recommended to have a separate ground trace directly from the converter to the power-supply entry or battery connection point. The ideal layout includes an analog ground plane dedicated to the converter and associated analog circuitry. From the ESD protection point of view, provide more ground vias to the ground plane right below the TSC ground and the TSC power supply bypass capacitors. At least one ground via per capacitor is recommended. Sharing a single via among multiple capacitors needs to be avoided. It is important to ensure there is ample ground path to the system ground to allow ESD discharge current if the touch screen subsystem is implemented on a flex., Y/ z& u& k0 x$ y# t
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