标题: 错误之Page 2 cannot be saved as logical page 1 has different page mapping... [打印本页] 作者: iseariver 时间: 2015-10-13 16:33 标题: 错误之Page 2 cannot be saved as logical page 1 has different page mapping...
) t' |) [& e' D- n0 @2 h3 u采用Allegro 16.6，( a1 x! p7 b3 D/ D" u
保存有个错误，如下： 1 K' ]! k1 c' i1 A2 y: s9 z Page 3 cannot be saved as logical page 2 has different page mapping in connectivity data , @( g4 D3 ^8 Y7 Q+ R4 k [ |+ x" D ( T. L+ F% U! `/ s % v j# M! b' T, T同时，网表输出不了PCB文件。谢谢，在线等。。。5 a+ h# |; \; W2 i" y# Q! N 作者: kinglangji 时间: 2015-10-13 16:53
真心没看懂...HDL原理图?作者: Emerson 时间: 2015-10-13 17:16
同不懂 坐等见过的~作者: Larry_11844 时间: 2015-10-14 10:26
坐等大神回答