标题: SPB16.60.057_wint_1of1.exe [打印本页] 作者: zgyzgy 时间: 2015-9-13 16:53 标题: SPB16.60.057_wint_1of1.exe 本帖最后由 zgyzgy 于 2015-9-13 21:16 编辑 % I6 h( r3 i( l* k/ x! M/ A6 h$ t N# B5 E) t' V% ~/ l5 dDATE: 09-4-2015 HOTFIX VERSION: 0577 T/ }: ^$ b5 [. |# V( w
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CCRID PRODUCT PRODUCTLEVEL2 TITLE1 G4 H' c$ f! ~) N
=================================================================================================================================== & x% a6 R! W2 P5 T' u; \4 U# N# N1249604 PCB_LIBRARIAN LIBUTIL Libexp verify runs both con2con and hlibftb - G3 a( O1 _+ z" r l Y8 h- {8 q% v1417327 CONCEPT_HDL PDF Omit mechanical page while printing PDF; L0 S. l: H" D4 d
1440484 CONSTRAINT_MGR CONCEPT_HDL existing pcb diff pair name is changed by netrev 2 h+ z$ g& A/ C" a1441086 PCB_LIBRARIAN OTHER Cannot delete pin & added pins change after save, y# ~& r$ L0 I( x& f: P" X% i
1448066 SIP_LAYOUT TECHFILE Using a script to export technology file from Constraint Manager crashes SIP_LAYOUT# k- w: n$ f% ^: f& N( [
1452431 CONCEPT_HDL CORE Obsolete $PNN is remained in a dcf file and Attributes dialog * v; ^1 Z u* r; L0 x: \1452640 ALLEGRO_EDITOR OTHER Updating PCB Board file concern; E# k" C2 m1 M) ^3 Z3 q7 _
1454730 CONCEPT_HDL CORE Zoom/Pan Disrupts move and copy6 G( y& t4 r. p4 {* c( L+ ^
1457713 ASI_SI GUI Setting Sigrity_EDA_DIR for Sigrity 2015 /OrCAD ERC ; y6 v5 b1 b% d1458439 F2B PACKAGERXL The Packager pstprop.dat file reports false conflicts in net properties 3 W0 N- W4 V: q B1458461 F2B PACKAGERXL The pstprop.date file "Conflicts on Net Synonyms" are NOT reported as errors ' W: C, z" s5 w) o( ~! S0 w7 z1459153 SIP_LAYOUT OTHER Mirrored components with pads on diestack layers (above top/below bottom) display on right layer but aren't selectable. 7 d7 Q2 [( L n/ Z1461553 CONCEPT_HDL EDIF300 edif300ui writer crashes on ADW design" s2 g0 x9 h/ Z- e2 P
1462254 ASI_SI SPDIF Ball properties are not translated to XtractIM using SPDIF& }1 `5 k; Z; V# @. P
1462441 CONCEPT_HDL OTHER Pin text alignment and overlap with symbol boundary issues on symbol rotate 6 ]" U7 e w9 _7 c1463333 ALLEGRO_EDITOR INTERFACES PDF created using Export > PDF shold not zoom to Page fit when selecting another layer$ K$ b# p& q3 z9 \6 s }1 F
1463358 ALLEGRO_EDITOR INTERFACES Color assigned to pin not passed to PDF& r& X/ V7 s" p+ t, \# b; }9 g
1463648 CONCEPT_HDL CORE Need ability to block the uprev of a design & q! U2 G. n$ }3 t- c: l8 I: z1463839 APD OTHER Changing DIE property to another layer does not change its masking layer " H# h4 ]: v H- z1464380 APD OTHER Why pad at wrong layer when we place SIP 16.6 but 16.5 is correct.: @/ V# y0 O3 T0 e; u" ]$ |
1464660 CONCEPT_HDL CORE Problems with "save hiarachy"' v: P. @4 o {9 r) X
1464771 SIG_INTEGRITY OTHER PCB SI crashes when extracting differential pair topology from Constraint Manager# q; w% R, n ?
1464909 APD WIREBOND Bondfinger drifting off of the WB guideline+ `: L0 d2 [2 M% q
1465273 SIP_LAYOUT STREAM_IF Streamout with mirror makes die symbols not located at where they should be in gds4 S% z' }+ j* L7 O: A
1465457 CONSTRAINT_MGR CONCEPT_HDL Layer characteristics from a lower-level block are merged with the higher-level * V$ |9 R6 `6 h' `: g8 i J( j7 R. V1465541 CONCEPT_HDL CORE CM_VALIDATION_ON_SAVE is crashing DEHDL on startup8 l7 M \5 o, _- t! q$ U
1465543 F2B PACKAGERXL USE_PACKAGED_NAMES is crashing Export Physical: P5 |" W$ f0 e! e, ]! t, T
1465911 CONCEPT_HDL OTHER Question about checks made in HDL while creating BOM7 z$ A& g# e+ ~
1465916 F2B DESIGNVARI Issues with variant management in ISR 055 #1 - Must save variant in Variant Editor to add info to CPM 0 i F: _4 j6 R! I7 t7 X1466230 CONSTRAINT_MGR UI_FORMS The Clear option is missing from the Reference Electrical CSet field in all workbooks5 a R" z4 m- a+ l6 l8 m: r$ ~
1466404 CONSTRAINT_MGR ECS_APPLY ECSet mapping using tags not working" C; A+ |5 P) Q( D4 S b j& ]3 E
1466492 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when using the Add Connect command 2 Y" l* Z+ e/ z1467156 F2B DESIGNVARI Out of sync endless loop 1 n t" |% S0 T5 t7 H, [ Z1469062 ALLEGRO_EDITOR EDIT_ETCH Crash while performing neck mode for Diffpair' b, a5 h( Z2 |/ X; u
1469081 ALLEGRO_EDITOR ARTWORK Short in Gerber Data due to wrong cut out around via/ D+ {2 B2 T1 m$ _; b4 V9 `- ~1 E
1469713 TDA CORE Updating project with non-existing variant crashes TDO - l3 ^' p; r( L # A( G# e$ e5 H正在上传文件中，分享链接稍后。。。。。。 7 n. M. n9 S, m" j: `) a1 N( m+ X/ n* F2 R0 H$ g, U/ z+ I: b
http://pan.baidu.com/s/1qW3jhoC ( ?1 R& ^1 h# N作者: yilongshishui 时间: 2015-9-13 19:47
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