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标题: split/mixed 层 导gerber 出错 [打印本页]
作者: dengzs2008    时间: 2015-9-1 08:52
标题: split/mixed 层 导gerber 出错
本帖最后由 dengzs2008 于 2015-9-2 16:52 编辑
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6层板，原先都是 no plane 层，做过一版。在原来基础上 top 和bottom是no plane层，中间四层改为 split/mixed 层，在lay完板后，规则检查，连接性是没有错误的，但cam中导gerber出现莫名其妙的错误，导中间四层时，会出现以下错误提醒。: o; z8 g1 |  ^& l4 ~

! C1 i* X+ V6 {9 IClenrance checking has been done for the entire design3 H( m& k2 _  {! j5 l% t
**NO ERRORS FOUND**
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Latium design rules exist.
; Z) y' s& [* |- |( FRun Latium design verification form Tools，Verify Design' d! N. T! G# x* v9 O" P. L7 r

/ V; [4 A2 W$ [% G" l' h7 yConnectivity checking has been done $ u* E/ V9 L, i* g# r
Number of errors found ---36& O5 h8 }; s6 J
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0 W8 h$ p/ h0 P1 `* x奇怪，为什么在规则检查不出现连接性错误，而导gerber时，提示连接性错误？% ?- h# z5 `" t1 t8 H9 g' D
很不能理解，求解释，谢谢，不知道为什么传不了图片，能传的时候再传！
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作者: binshenliu    时间: 2015-9-1 09:24
可以忽略。如果觉得不爽就设置一下。
作者: jimmy    时间: 2015-9-1 10:13
上传不了图片，可以上传文件。
作者: dengzs2008    时间: 2015-9-1 12:34
binshenliu 发表于 2015-9-1 09:24
0 A* \9 H+ [+ `7 B* w" Z- O6 i可以忽略。如果觉得不爽就设置一下。
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确定忽略没有问题？怎么设置才不会提醒？% H# P' B6 @/ y- v
作者: dengzs2008    时间: 2015-9-1 12:36
jimmy 发表于 2015-9-1 10:13& S- h0 [% a1 J, z+ u$ g% v
上传不了图片，可以上传文件。
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现在可以传了，版主，请看，谢谢
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2015-09-01_083454.png
作者: jimmy    时间: 2015-9-1 13:21
看图片猜谜？
作者: binshenliu    时间: 2015-9-2 09:44
dengzs2008 发表于 2015-9-1 12:347 z" i( x5 |. f0 H
确定忽略没有问题？怎么设置才不会提醒？

; v8 h" F$ B% d0 V) c' Q没有问题
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作者: dengzs2008    时间: 2015-9-2 15:19
dengzs2008 发表于 2015-9-1 12:34
  M, q% F# h9 p确定忽略没有问题？怎么设置才不会提醒？

% O0 y$ g% T; k  ]怎么设置才不会提醒？求解，谢谢！
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作者: binshenliu    时间: 2015-9-2 16:25
本帖最后由 binshenliu 于 2015-9-2 17:35 编辑 . Z9 P! z5 ^* |4 J3 U8 L% M: g0 ~$ v
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你同一网络分割了几个吧。
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作者: dengzs2008    时间: 2015-9-2 16:54
binshenliu 发表于 2015-9-2 16:25  A) a) C  J0 y
看图

6 n* y) k+ B3 ]% b, l% O同层连接性检查。有混合平面层的PCB板，要做plane检查，为啥要把这个同层连接性检查去掉呢，去掉和不去掉有什么不同啊，亲( I' D$ {( j  {% `
作者: dengzs2008    时间: 2015-9-2 18:23
jimmy 发表于 2015-9-1 13:21$ r/ E4 R5 X6 {+ M& ^, d
看图片猜谜？

( @+ P- Y' L8 N1 h) l0 Y版主，看看老外的回答和binshenliu 是一样的处理方法。# t4 @) D4 ]& ^, G
问题：/ x/ Z! l1 j7 s8 u+ |8 ^2 d
DRC errors in CAM, but not in Verify DesignWhen I run Verify Design in PADS Layout 9.2, clearance and connectivity check out fine, but when I run CAM, I get errors.  I have no way of knowing WHAT those errors are; error markers are placed on the layers, but are they clearance errors? connectivity errors? And why would there be different results in CAM than in Verify Design, don't they use the same Design Rules?' T/ C+ k: c2 P+ }- }8 u+ o

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# I( E& P8 R6 l: X回答：If your CAM documents include Split Planes, CAM will automatically perform a Plane Check as defined in Tools > Verify Design > Plane.  The settings for your Plane check may be incorrect.  Go to Tools > Verify Design > Plane, click Setup. Set the selection like the screenshot shown./ n9 r( f& a0 j
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总结：Okay, folks, here goes.  Thanks for all the suggestions; by putting them all together in a blender, I think I've found my problem(s)( m7 B2 D/ }) b  {8 P

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1) I have multiple planes with duplicates of some of the nets on multiple planes. So, I would end up with plane islands on one plane, but it didn't matter to me because connectivity would be made on the other plane
2) When you run the "Connectivty" check, it verifies that all signals are connected, without regard to which plane they make that connection on.  BUT, when you run the Plane check, it looks for islands and flags them as an error. (This was my main problem)
3) I have two separate planes on one layer assigned the same net.  They are joined together on a different layer.  But, when I ran the Plane test, it saw the two separate planes as an error.  The only way I can get the error to go away is by adding a "dummy" trace connecting the two planes.

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Thanks to all for helping me to see the light.
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Barry

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