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标题: SPB17.0BUG讨论贴 [打印本页]

作者: steven.ning    时间: 2015-6-22 08:26
标题: SPB17.0BUG讨论贴
发现一BUG:用ALLEGRO17.0 PSPICE仿真时会无故退出。不知破解的原因?还是什么?
作者: pzt648485640    时间: 2015-6-22 11:29
补丁打到多少了呀
作者: steven.ning    时间: 2015-6-22 11:36
002
作者: steven.ning    时间: 2015-6-22 11:39
BUG二:PSPICE仿真后,波形都出来了,用SU标点一下波形,软件自动退出,重新打开不能再仿真,只能重建仿真项目。
作者: pzt648485640    时间: 2015-6-22 11:42
steven.ning 发表于 2015-6-22 11:36% j$ Z2 q7 o) g$ E2 I, b$ R2 s
002

- A" H# I1 f. f0 o4 Y打下最新补丁试试;有些问题主要来源是破解问题造成的;Cadence软件来回效验好几次; T! m' ^5 i. |
DATE: 06-5-2015    HOTFIX VERSION: 003+ U/ V# f2 S/ K8 i( c* c( O7 }
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6 h2 f" E5 \9 l& Q/ }CCRID   PRODUCT        PRODUCTLEVEL2   TITLE4 P" b. U; y# s; N& n: X- M, G
===================================================================================================================================9 k& q9 ?# f/ C! |2 l7 g
295747  ALLEGRO_EDITOR PLACEMENT        Place manual form takes a long time to open" R, K, ~" H  G
832170  SIG_INTEGRITY  SIMULATION       IBIS buffer results with two TV curves do not correlate with HyperLnx or MATLAB results5 j0 c& f! v$ v
926138  SIG_INTEGRITY  SIMULATION       IBIS buffer results with two TV curves do not correlate with HyperLnx or MATLAB results
$ @2 H2 i* R& C: q# j( X0 w5 j1306988 SIG_INTEGRITY  SIMULATION       Support needed for the multiple VI and VT waveforms for the buffer with TLSIM1 @1 z7 m; K: D  y9 w" n. c& R
1376591 ALLEGRO_EDITOR COLOR            Dehighlight command with "Dehighlight All" option does not remove the color marker swatches from Constraint Manager9 N7 _% g' R$ r# Z5 R/ W: `
1379188 CONSTRAINT_MGR INTERACTIV       PCB Editor crashes when opening the min/max delay worksheets in Constraint Manager6 h/ O0 U1 W) S
1397823 ALLEGRO_EDITOR MANUFACT         Pass property for shapes defined as Fillets in IPC 2581 output
& Q* \# ], {6 C6 J% i! t1404858 CONSTRAINT_MGR OTHER            ERROR: Can't import electrical constraint data (pstcmdb.dat)
& o/ ~1 i2 W0 }2 \" @# K5 n1405333 CONCEPT_HDL    CORE             The Edit - Search - Option command  (Find) does not work in LINUX
8 M. F! w. V' F9 K: k1406666 CONSTRAINT_MGR SCHEM_FTB        Add blacklist and whitelist support to diff3 reports, o, i4 j8 x! I) Q4 X+ H: {2 I6 Z
1406780 CONSTRAINT_MGR OTHER            Deleting cline segments when Constraint Manager is open on net properties bundle crashes PCB Editor# q* `  F2 z/ U' F1 p
1411637 SCM            SCHGEN           Incorrect Ref Des in the flattened schematic generated by exporting from System Connectivity Manager
9 _; i- ]8 P" J$ Y4 t3 I1415205 CONSTRAINT_MGR OTHER            Constraint Manager only stores the last resolved analysis when formulas are entered
; P+ d: y. i' U: w1416059 ALLEGRO_EDITOR PLOTTING         Some of the pins are not visible in the  PDF generated by Allegro PDF Publisher* I3 X: H+ b8 f: f! O
1418484 SIG_INTEGRITY  SIMULATION       Estimated Xtalk and Simulated Xtalk results do not match in 16.6 ISR0447 b/ l/ [2 [) A, j" D+ _: }
1419041 ALLEGRO_EDITOR DATABASE         DBDoctor removes tapers and displays ERROR(SPMHUT-17) and WARNING(SPMHDB-391) messages
6 H) Z2 }4 |2 R- p5 Y5 H- c3 i% q& |1419995 SIG_INTEGRITY  OTHER            Model assignment auto setup does not use refdes when determining what type of model to create7 m: `- C" S: y1 Y+ d
1420551 CONCEPT_HDL    CHECKPLUS        Rules Checker (Checkplus) crashes when a part is missing from the library
; I* ?$ |0 m& f! |7 y* F6 e! r1420580 CONSTRAINT_MGR INTERACTIV       Constraint Manager crashes when displaying the Relative Propagation Delay worksheet
1 q- N  \7 ?% N. M" w2 w* Y/ E4 H' @/ _1420623 CONCEPT_HDL    CREFER           creferhdl fails with message std::bad_alloc on Windows and Linux
( r/ d) ?' Z1 C! }- V1421769 ALLEGRO_EDITOR MANUFACT         NC Drill legend behavior changed from S040 to S048
0 q$ M, A! }# _. _: @1422153 CONSTRAINT_MGR OTHER            The display in cmDiffUtility is corrupted after a Match Group is removed
  f2 `+ y" x9 E1 D" `3 i1422993 SIP_LAYOUT     DIE_STACK_EDITOR Diestack Editor graphics depicts die stack incorrectly. The complete stack isn't shown
7 }6 m" \, ?- p, h8 v1 ]. j1423988 ASI_SI         GUI              DesignLink system configuration file is not set automatically on SI-Base; z: T2 f% R: K0 [( e

作者: steven.ning    时间: 2015-6-22 11:47
已经用回16.6了,过段时间再折腾17.0.
作者: blueguyhk    时间: 2015-7-7 15:38
本帖最后由 blueguyhk 于 2015-7-7 15:40 编辑 4 w5 _6 R( y# G; R. `. m' c

+ h1 h. e8 U6 D  ]這兩天在試畫,確是常常無故退出(pcb editor, spb17.03, win8.1)
作者: blueguyhk    时间: 2015-8-18 17:11
本帖最后由 blueguyhk 于 2015-8-18 17:45 编辑 7 g# E& V1 K2 S2 f% @* C& ~
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spb17.0真的很小人安装.....
- f) M* ]) h' [% G% V请教capture 与 allegro交互在"新进行" "create netlist"后就可"交互", 但关闭重开程序后就无法"交互",这也是17的"bug"?......win8.1/64, 已装hotfix05   >.<




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