EDA365电子工程师网

标题: 对这段文字描述感觉有些困惑 [打印本页]

---

作者: mengzhuhao    时间: 2007-12-21 18:01
标题: 对这段文字描述感觉有些困惑
对这段文字描述感觉有些困惑
0 H& Q$ u) [/ N8 ]
! V' Y( v1 J$ @) j4 n  Z+ R1 g1 M
. @: E' h& U" v& F4 x5 D# H8.0 Actual "full_case" design problem
The 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
any synthesis directives. The resultant design was a decoder built from 3-input and gates and
inverters. No latch is inferred because all outputs are given a default assignment before the case
: ~' ^  O9 h7 p- \% J1 gstatement. For this example, the pre-synthesis and post-synthesis designs and simulations
matched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
# P0 A# g, S( \"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
optimized away during synthesis and left as a dangling input. The pre-synthesis simulation
results of modules code4a and code4b matched the post-synthesis simulation results of module
code4a, but did not match the post-synthesis simulation results of module code4b [2].
// no full_case
// Decoder built from four 3-input and gates
// and two inverters
module code4a (y, a, en);
; O- Z% A, D  X4 _output [3:0] y;
input [1:0] a;
, b3 i  ]; i+ `! }& E% d6 l  F- `6 c0 xinput en;
* E+ C9 X, v4 e- D! oreg [3:0] y;
always @(a or en) begin
y = 4'h0;
case ({en,a})
! x. o) i0 H  u1 c' z7 u% F3'b1_00: y[a] = 1'b1;
3'b1_01: y[a] = 1'b1;
3'b1_10: y[a] = 1'b1;
3'b1_11: y[a] = 1'b1;
* j" O/ X1 `3 A& |endcase
. R, }! }- V6 G7 F0 k- ]end
endmodule
Example 12 - Decoder example with no "full_case" directive
# u- I! w& v1 hStatistics for case statements in always block at line 9 in file
- J! G+ R1 J: T  l# E'.../code4a.v'
0 O, _& B- S4 t) I  ]/ t===============================================
| Line | full/ parallel |
) F. u. u1 t1 \* \% l===============================================
| 12 | no/auto |
===============================================
Figure 19 - Case statement report for Example 12

* V0 d. T* ]! M1 g; D/ y  {7 T
8 [/ R6 o- ~0 E( }' c// full_case example
// Decoder built from four 2-input nor gates
+ U8 y+ w: i% o; u// and two inverters
0 L/ i+ B" I* J' z% C8 n1 _// The enable input is dangling (has been optimized away)
module code4b (y, a, en);
output [3:0] y;
input [1:0] a;
input en;
0 `; [* E8 ^$ ]$ L* v( \reg [3:0] y;
" q# h! C. ^  Q& i, |5 @' `6 Malways @(a or en) begin
y = 4'h0;
) _! y1 W# Z2 J0 g3 hcase ({en,a}) // synopsys full_case
! v( v+ f1 P4 l, o8 s3 H! p3'b1_00: y[a] = 1'b1;
4 ~8 g, N% c; S' T, c7 d; n( ]5 E- n3'b1_01: y[a] = 1'b1;
3'b1_10: y[a] = 1'b1;
3'b1_11: y[a] = 1'b1;
2 Z- f6 X; ?. m2 U) t+ T) lendcase
end
endmodule
Example 13 - Decoder example with "full_case" directive
Warning: You are using the full_case directive with a case statement in which
0 M+ X% o: b7 X  c1 }not all cases are covered
Statistics for case statements in always block at line 10 in file
) C2 X$ d6 U6 ^" y/ T+ c: V  E( {'.../code4b.v'
* k8 m0 I" v. ?( `) ~6 v===============================================
| Line | full/ parallel |
- l  o# F+ t' g===============================================
| 13 | user/auto |
===============================================
6 q. J: x/ w+ {5 ?5 PFigure 20 - Case statement report for Example 13

0 h- I. b1 m8 p. S+ _2 E谁给解释一下原因呢?
) ~( L6 I, P/ e0 l: c为啥会有差异?

---

欢迎光临 EDA365电子工程师网 (http://bbs.elecnest.cn/)

Powered by Discuz! X3.2