! e/ V7 m* C3 _7 h: Y5 U( l/ U: x , A) f; P5 N$ @) t! C) sAltiumDesigner15.0.7出来了！ 5 u' E$ y. I. ^1 R我唯一的感觉就是，Altium，你更新的太快了啊！有事没事，你就更新，/ N) D' o! i9 n9 R
或者说是，你是在修Bug么？？/ c; O7 n0 l# }* X1 T1 J: ?
貌似AD14就一直是Bug不断，这次AD15估计也一样，不过， 2 r, I7 q, |4 P# \0 ^: K: r1 ]貌似AD15更新了高速PCB设计和GerberX2的支持。具体更新如下。. R$ ?. S5 Q. ^. n: e
就一个问题，AD总是在不停的更新，是表示软件不稳定呢，还是？？？ : q& P- ~# ?8 T: |或者说，你会更新到AltiumDesigner15版本么？ 6 A4 Z7 s3 e( k% M* j2 k' s0 K2 {1 T$ W6 V) c9 T Release Notes for Altium Designer Version 15.0" V2 `( N) S! d' A
Modified by Nikolay Ponomarenko on 17-Nov-2014 ) ^, s5 A" D6 K- h, S" HKey feature highlights3 A. i( L1 q1 r- n4 n High Speed Design with xSignals2 c' Z2 R2 g4 V, t0 l4 @& Y. n Solder Mask Expansion Enhancements 6 z8 H$ T8 A; Q6 t! V, R8 e3 [Accurate Route Length Calculation( }3 j* f' `% j4 `9 b: b Polygon Enhancements$ @7 Y* p1 }; r2 C* g OLE Object Support in PCB Documents - j2 d1 z% j, y" n$ O& U4 h' bSupport for Rectangular Pad Holes8 c# N: ~" L, o, |! ]9 Z Separate 2D & 3D View Orientations & ~: O1 E0 S7 L( T7 eIPC-2581 Support H @8 I8 c" M' PGerber X2 Support , j% N0 `, X* y0 R8 J. ^# J0 |4 lIDX Support ) O @4 Y3 Y& ~" l+ S9 z; ]Exporting to IDF in Unicode Format# C+ g! H& }! d1 b- J: ?/ t True Variants Enhancements 5 ^5 c; ^, q% w) \Output Job Editor Enhancements ( I' [+ c. b9 Z+ q1 bUpgraded Duplicate UID Correction4 ?1 Y/ a! V8 ?, S- t System and Performance Enhancements/ U; q# Y* y, V( s) M/ M Vault Connection Enhancements/ L+ C4 u8 \7 M4 N) o Ability to Control Parameter Visibility for Vault Components8 t1 \( W/ ^$ B" t Parameter List Templates; z5 I1 C0 ?3 ?' T: s5 j( u Parameter-based Name Templates 7 R9 w$ W* V1 b' jVivado toolchain improvements2 d/ Y. Y6 i3 _3 i; o* O Intuitive Import and Export; K5 y& @, e4 _3 j* ] Version 15.0.7# N/ z( ^9 |7 V9 Z' m Build: 36915 Date:17 November 2014: W/ ?- n3 k/ |6 a9 R( J4 o
1015 Support for high DPI screens using oversized fonts has been reviewed and improved.# l+ e: _1 r% `# a. q4 W) h
1335 PCB NC drill layer pair reports now correctly report layer spans for blind/buried via holes,9 u- O m. E8 K0 [
when layers are shuffled out of default order.; V: F* @) i7 h3 Q! S! O& s
1381 Export to AutoCAD now correctly includes thru-hole pad geometries and holes." L0 c/ K) B1 G% c
1382 After certain editing sequences the PCB editor would incorrectly switch to masking the display, : I5 B( V. r# F# J, E$ N0 ~this no longer occurs. ) q: A! ?5 W& K: x- `# d+ G( D1 D1408 IDF export now includes an option to export in Unicode format. 7 u" c* {& d }/ u( G4 K1615 Changing PCB layer names could result in layer-related lists populating incorrectly and certain- f$ {+ N# N" o" }! a: Z6 G/ X) V
outputs not generating correctly, this has been fixed. + G H, l3 D R" t- ^! |2 h2613 A Vault Content Cart can now target regular folders.( k/ ?* W: n e2 k. g8 ?
2816 It is now possible to define a CmpLib Component Naming scheme using a template with , C7 Y' @% y; s' X$ Pvalues from any parameter, for example CMP-[Value]-[PackageReference]-{0001}.# Y& n v+ M8 d1 m# z$ f
2817- E: u. g* f$ t( v% L2 G9 U
The CmpLib editor now supports the addition of new parameters via customizable parameter ) O/ B' `4 `) llist templates. Click the Required Models/Parameters Add button to access the templates / q" D. [, a7 P(samples are stored in the \Templates folder).8 V/ S6 S" g( ^
2855 Duplicate UniqueIDs are detected by the Schematic compiler and detailed in the Messages ) i B/ u' O9 I! K9 _panel. Existing duplicate UIDs are also automatically resolved during document loading.5 B0 C! |" c. n: g G3 n1 g% L
2910 Release Notes column is now available when using Vault-based libraries in the Libraries panel. % Z4 g2 D" \) N( j2 h& _& n; M3006 The Component Cuts Wire mode now functions correctly when the Always Drag option is8 m9 W$ b3 K4 e6 x+ X9 U) M
enabled. 5 U! O* w9 D8 q30081 ]1 F; W! }5 O4 I7 U
OutputJob Editor enhanced by the addition of: mouse wheel scrolling & scroll bars when not ; s% T; w P$ |all Jobs/Containers are visible, drag and drop to change Job order, multi-Job Enable/Disable4 Q8 C4 l' b* b1 m- m. i# }! g
right-click commands & shortcuts (select the container first).3 z5 p" }% e+ G
3026 Import and Export options are now directly accessible via the Files menu. Save As commands0 \8 b" H& i) L* V* C5 o8 R' I
are now used exclusively for Altium file formats. (BC:1812, BC:2731 partial)7 d$ p. L0 V! k% K; } m
3033 Gerber X2 is now available as an output format. It supports output generation via the PCB8 w3 g9 J7 b0 Z9 r* m
editor Fabrication Outputs menu, or via an OutputJob.9 C% Z! ?8 w8 k" h5 _& C( \2 T
3035) v) f- c" i' W* |) H& M
IPC-2581B is now available as an output format. Install the extension and generate output via * I1 ]$ @+ {; _, m& @the PCB editor Fabrication Outputs menu, or via an OutputJob. Download a free viewer from ) @6 k! Q3 I3 ehttp://www.ipc2581.com/index.php/ipc-2581-files 2 N9 _; x7 u$ s3081 The Vaults panel now supports changing the column visibility and order. These changes,; R" [! [: c) A: z5 Z
along with panel-section resize actions are retained between sessions. 7 o% n# J0 p" s, C5 Y( _3143 Timeout errors after releasing project documents to a Vault have been fixed.' r. B# b" j& D! ]: T- v+ W
3188 OutputJobs now support using a slash character in the Output Container Name.2 L2 c! X% J8 e, O$ D) F( `
31899 T- @" A( s$ x' t0 T/ _
It is now possible to pre-configure the display state of Vault component parameters, via the 9 o5 @$ F! C" j8 o- b' C* ]Vault Folder Properties dialog (Type = altium-component-library) and the Vault Library dialog : G# }+ c& O- U3 C2 ?(add a Vault as a Library).! U+ K4 @4 m3 W, V# C$ V
3205 Switching from the logical to the physical tab of a schematic no longer leaves artifacts on the6 {7 D8 Z% J4 l0 h! h' I
screen.+ S" y0 v) e& r, B7 M- c# |
3225 Schematic dragging has been further developed to improve wire/bus bending and reduce the 3 q3 F2 G% b* N" \4 e1 {likelihood of a netlist change.3 Y4 ~( J! A: n! n3 x, B- G; G
3227 Schematic dragging has been further developed to improve object handling and the quality of : q9 G& U6 u8 H; z9 q- f; qthe result, and reduce the likelihood of a netlist change. ' a9 }" F3 M0 F. ^0 m; _ e0 X' ^3232 Polygon vertex deletion using Ctrl+Hover+Click is now working correctly. Hold the left mouse 5 W [( s3 K1 f/ k2 u* b3 Hbutton down as you click, until the vertex disappears. 6 o8 p1 p/ \9 v5 H- \# S3251 Releasing projects to the vault with file-locking being enabled works correctly now ! X% n% \! n7 L! Z. R8 J8 {" D3272 The schematic library editor panel now supports standard copy and paste shortcuts, Ctrl+C 3 d% m4 }* f+ A; F7 f9 f7 P5 Iand Ctrl+V. ( s- i0 v( j& S6 r! ^3293 BOM filters no longer mix up the parameters. Note that for an existing BOM the filters must be# X/ x+ Z1 \" W; y
cleared, the BOM saved, closed and re-opened, and the filters re-defined. 4 y8 j# y$ Q4 A) Y3338 Multi-net routing no longer creates a clearance violation at corners when the Converge+ ~( Q6 A- v3 b/ V6 D* I5 I- S) ?
shortcut (C) is pressed. 3 V g0 e2 P j8 E3341 When a PDF is generated from a schematic that includes a hyperlink, clicking the hyperlink 7 x- A# B# b0 C0 ]- R3 Onow opens the target web page correctly. G9 [- B4 ?; U8 J J" H
3357 Teardrop removal speed has been improved. 9 s7 p+ q5 M& a' o7 S# B3381 Second click to select an individual segment in a schematic wire now works correctly. 3 V6 `' V/ x9 x& r% A3412 The issue with not being able to close documents having "=" character in their name has " ~6 d+ \, ^ G1 J; m# {3 @been resolved $ a1 k3 m k- |) |3419 When the Interactive Router is in push mode, a via on the pushing net can push other-net9 O) f# U7 {4 f- [/ K
objects, including vias.& ]7 y( h2 G) Q
3423 A specific Verilog HDL project would cause an AV on compile, this no longer occurs. 9 d# u* U# I; E, a, g3425 Update from Libraries now correctly preserves existing location and orientation of parameter' R. \/ D: Z& F( i! F
strings. 8 T3 s( u; `3 n5 S* j6 z v& X8 f3437 2D and 3D PCB view orientations are now completely separate, each retains the previous & W. J4 B( h- `7 J }4 `: a0 Yorientation and zoom when switching between the views. 9 w( \4 T$ A% X1 \/ b8 U5 w. f3441 ( g3 `" K. H7 k/ YPin-pairs have been added to the PCB editor, delivering the ability to define the path and. \8 ?, v8 e& i6 v2 g
constraints for a signal to travel between a source and destination, through termination$ Q) J9 e T/ [0 C
components and y-splits. , y( V) C }2 f8 Z3 X3442 The import of complex arc shapes from AutoCAD has been improved. 5 p' b. x2 V8 t! M. ^" c4 L3443 The PCB Editor now supports embedding OLE objects, such as Word or Excel documents, into& v- y! Z6 `, z
a PCB document (Place В» Object from File). / M; D0 ?" Q0 a! y% O1 Y3456 Xilinx Vivado toolchain is now correctly detected, and can also be added manually in the FPGA 9 _+ {' V" e ]4 Q- Place and Route preference settings.$ r( l2 W) p \- @8 {
3457 Split plane editing could occasionally cause an exception, this no longer occurs.- a; M# T) I% J1 v, s9 N
3459, L, |: N# T8 `# n
When a wire is placed perpendicular to multiple schematic pins and then dragged, a wire' N% x/ {3 s6 C; S% |: I
segment is automatically added between every pin and the wire being dragged. This fix " o! {- S7 u+ ^3 Y% b' wrestores previous schematic editing behavior.2 h3 G. W u$ Q1 u- q$ m( e# y
3477 Schematic library editor, the Parameter Manager now supports editing parameters across 9 D5 u" ^1 |$ M/ Fmultiple selected components. # m0 H% L. R2 `3492 A warning is displayed when you attempt to complete an invalid blanket (has intersecting. O. ]& O6 p2 I6 W3 y. S9 y$ t
edges) in the schematic editor." s4 k! Y& @) I$ V& w
3495 PCB component fanout now functions correctly when there is an unpoured polygon under the + s. H3 l' M6 c5 F8 \( F Bcomponent.: |/ B5 u# E/ \1 ~1 N9 w# U. N
3497 Click and drag to move a group of selected objects now be functions correctly. x9 O- g n4 _) ]3498 An exception that occurred during import of specific DxDesigner projects has been resolved. 7 y! [! i& w0 S, b3514 PCB Step model import has been enhanced with better support for curved shapes. ( ^; G* g6 Z/ E i5 X3521 Fileless editing of an external SIM model no longer generates an AV.8 ~1 B7 [+ |8 ]7 q5 J6 R9 c
3528 AVS 1.1 is now supported by Altium Designer 14.3.1 D( M1 B9 H# k, L( F6 I
3529 Component pads placed on a signal layer other than top or bottom could not be edited in! ?3 }+ e8 V# [- ?/ S9 |
certain layer-stack configurations, this no longer occurs. % E+ D- K' T- U9 Z4 v3530 Top and Bottom Solder Mask layers are now included in the PCB Filter panel's Layer list. 6 f' ^: L. ?! x3 F) y- J4 ^: _3546 The IPC Footprint Wizard now previews 2-pin and 3-pin DFN component correctly.* w7 B2 F2 o: X! N5 a" V
3551 Schematic auto-junctions now size correctly regardless of the wire width. 4 u6 b7 @( U0 B& Q! s7 ^* g3556 Component primitives placed on mechanical layer 17 or higher now have their layer displayed8 _* @7 F5 O& E* H; ` U; w0 x6 F
correctly in the Components mode of the PCB Panel.( [ X5 Q$ Q- R- W5 O3 Z7 q
3560 It is now possible to connect to an SVN repository with a user name containing the @" D4 T! U* }; F" L! ?8 `0 o0 f) w
character. 0 l% P8 A# p1 C$ K4 N, q# j! G. p8 Y3561 The correct Lifecycle and Naming Schema is now being loaded during CmpLib file-less editing. $ }' d9 f. }5 R3567 Model selection drop-downs in the CmpLib editor now display the Lifecycle state in color.# _5 I/ g, l; }3 Z/ t* Y
3568 The Vaults panel now shows the Note data from the correct Lifecycle state. 8 `: {) c0 ^% ~' B# X; }' B5 G3576 PDF generated by running OutputJob can be opened directly from OutputJob document) K ~8 T# j- J7 `# ~! X3 z
3577 Simulation model pin mapping now works correctly in the CmpLib editor. 2 t+ A$ |/ e" E3585 Pin swapping was not correctly generating an ECO after performing PCB pin swapping, this 7 ~& {$ V! C5 {/ l6 p3 r; ^ X1 jhas been resolved. * @; Z7 x" O7 P8 w3592 The path tracing routines used for creating a polygon from selected primitives have been: i! d1 p' h& E+ C
improved, to better handle small objects and multiple paths.$ O5 Q7 g6 n2 P7 B2 W9 p7 ^
3598 From-To panel now shows length taking via heights into account$ T6 N8 |( f' \6 k' }" W0 W* s
3611 The schematic Place Wire command now correctly retains the corner mode used in the ( b+ e7 B. S# H& }, s1 Rprevious wire placement.# a" U( Z0 \* [! s: E' U; L
3626 Vault-defined part choice currencies are now used in Altium Designer supplier dialogues% p" z, R$ I% o! ?, c& d; }
3633 Updating Altium Designer from an NIS no longer requires a current Portal connection. * H+ A+ P+ p3 j P) Y& f# I3634 "Access denied" error when installing an update from NIS has been resolved1 ?# ^/ ^4 t2 @$ ?( B$ c1 q
3640 Support for rectangular-shaped pad holes has been added0 A+ Z: l# _, {6 s7 [9 [, [
3664 PCB exception while re-building a net to an arc center point in a specific design no longer 4 \4 |( j2 ^) Q! e2 Koccurs.+ ]. I$ F/ I4 Y
3681 Plane connects (thermal reliefs) are now shown correctly when board is flipped0 x& H* N) S# A" }4 P
3689 Exception no longer occurs when choosing PCB font style in VariantManager (BC:4664)% ]) }; H( f5 k F# M6 _: p2 j
3692 Pads with rotated square holes no longer show copper still being present after running the5 U8 N, [* d; H( V P2 H" D
Remove Unused Pad Shape command.! z" [, i6 C, V4 }3 U
3695 GOST specific documents can now be generated in BOM Report outputs 3 O% C/ f$ y$ J w1 M3707 "No model link found for component" error no longer occurs while editing old cmplib files, t$ |, ^$ W! J2 z0 l, b L6 j3 f
3708 Clicking on a supplier part number in the Vaults panel no longer causes an exception.2 E+ k3 |: ~4 I- m
3721 Occasional exceptions during a print preview no longer occur.9 N: h g, `7 o0 _- I
3722 Under certain conditions changes made in the Variant Management dialog could cause an % |+ }7 s. Z* B; _& n6 R8 Vexception, this no longer occurs. % P$ H2 Y3 D2 X5 m3729 The Variant Management dialog now immediately reflects changes to components, such as 1 x7 b- A, Q- c g4 O4 Dclearing or choosing an Alternate Part, improving usability. : e' V3 c. x$ F. z# g3732 The Edit action is now available when right-clicking in the Search results panel in the 3 B' i) E' C9 T4 Y; PVaultExplorer 2 o+ w( ]1 \, X1 G% c3736 Fixed error while releasing Vault revisions with extra long file and path names- x2 E4 O7 e' ]* g, H
3737 Changes to Comment and Description are no longer lost during component release from the2 v: ~1 c, P4 [; i! T. T
CmpLib editor! q3 O ?" f9 `$ b
3739 A Length column has been added to the Primitives table in the Nets view of the PCB panel8 c2 v- U: Q2 }' O9 ?0 t0 z
3755 Scope section of the Teardrops dialog was modified to distinguish TH and SMD pads0 b- |$ C" ^3 n' A
3757 Duplicate Port UIDs no longer cause Port names to be changed when generating a PDF from, {" S7 i* l2 ^/ u
the schematic.3 i% n& z: j7 |+ p
3774 Under certain conditions, schematic compile masks did not exclude components or net 7 p9 ?- q) N9 v: h! {3 `objects underneath them, this has been resolved.0 t8 h. @0 J$ t/ T
3778 On a schematic with a lot of wiring, placing a wire with the Break Wires at Autojunction option 8 T3 h+ r: Q: G4 X2 K, {enabled was very slow, this has been optimized.1 J* c& _" L! }$ |7 l. Z
3779 Improved performance of selection and zooming in Schematic in comparison with 14.3- J6 T- O2 P9 D$ ^3 o
3785 Under certain conditions it was possible to get the PCB Layer Stack Manager graphical5 r4 w4 Y, H/ Y% U0 ~+ w5 v
representation out of sync with the tabular layer detail region, this has been resolved.3 |. x5 q/ }' w+ [- ~. G
3787 The "rint as a single job" option in Output Job File documents now properly combines the # O2 j. \# z9 R6 e& p" v. fseparate documents to a single print output $ L7 U# ~4 h9 G" o37899 t+ N, `' f9 I t J
PCB re-annotation on a variant design with not-fitted parts could result in the varied parts3 I: u! I V2 C9 d$ r
becoming out of sync, this no longer occurs. Note: PCB re-annotation on a design that uses& _; j5 b6 J% }
alternate parts with different footprints is not yet supported. . L* B/ G9 C$ p# T1 t$ R2 N8 G" T: \, d- I3792 STEP models from Inventor 2014 are now loaded without errors" w9 O8 g f+ n* s3 r f
3800 Variant PCB drawing options have been updated to make it easier to understand how Not: H% \) g V, K6 g& ~
Fitted components are displayed./ _ ~: f- L( }( \$ I
3809 It is now possible to specify different values for solder mask expansions for top and bottom 6 Y d* ^4 h* E+ ylayers7 R! M% ?) r5 w% P9 n
3834 Empty surface constructs are now suppressed in ODB++ fabrication output. 7 c. n4 t4 A K t. v6 \3835 The IPC footprint wizard now correctly supports defining PLCC packages with different D and E # w% s% D0 w4 d- e! i% Bpin counts, allowing packages with any even number of pins to be created.' v" u6 X$ l3 ]; N" [+ o$ L# `
3836 Dragging multiple schematic wire ends could occasionally result in one wire being shorter: _. F5 M0 h# u/ s2 ?! m7 Z. J
than the rest, this no longer occurs. : w0 D* }$ Z5 R, P4 t: }3841 Reset All command added to the Variant Manager, use this to restore all parameters to2 u+ h& ]' L+ t8 l/ x* J0 W& @
alternate or base component values. ( _8 ^/ j5 k0 e: ]3844 The issue resulting in "I/O error 103" error message when some of the project files are0 W/ R* S ~! w
read-only has been resolved: u& _% }) ~. D7 I; n6 B3 ^3 \" a
3845 The speed of updating from libraries or a database has been improved for designs that 4 ^/ E5 @! j& ]# m2 C1 `) Finclude variants using alternate parts.9 m' Q6 H, M, a! K
3849 In certain circumstances a component would still be shown as varied after resetting1 ~6 d# C3 ~1 m. E% `- n+ x+ z$ V
parameter variations, this has been resolved. 7 I6 ]: F) Z- x8 a- }, A$ U3857 Polygon management was improved in comparison with 14.3 (restored shelving, modified ; K" b1 \6 z3 ^# v% H6 _/ b9 Cconcept) 1 W3 q M8 W+ v l- F' h" O. S3 C& Z3875 The Vaults panel right-click menus now display correctly when Display scaling is being used. - \5 X+ G, A$ j/ L5 N3876 Elements of the Vaults panel were being compressed when Display scaling is being used, this& K1 Y: t: d$ \/ Y5 e7 A- I' v
no longer occurs. + a/ {% j: F/ B& z# Z+ P& [( ]3888 Crash reports can now be send from behind a proxy + D0 E1 g7 |& I8 ~7 W3 a, d: n5 l+ j3 G3889 Simulation Waveform viewer print preview issue has been fixed. & R7 U0 O! A9 G, O3900 Class generation settings are now stored for device sheets (BC:3840) 3 P% h5 |& R3 d* q d3903 The time to open the PCB Classes dialog has been substantially reduced, particularly on ) J& ^4 X& c6 H! j3 D B: V3 idesigns with a large number of classes.( O2 I2 T P K$ G$ W
3972 ODB++ output did not generate drill data for drill holes included in a panel, when none of the * {% z/ K( i" a Qembedded boards had drill holes, this has been resolved.* b# p1 r8 X/ }1 k' p- e
3984 Drawing of Schematic Blanket directives has been further optimized to get them to draw 9 r" ?% w" C. K5 I+ D1 B* m( x( vquickly and also correctly display the fill color. 5 c+ y: l, ?0 i" T: ]4005 Variant designs that include alternate parts with different footprints can now be re-annotated. G* R4 S- S6 o! J
in the PCB editor. , Y: J, v& U! A* I4016 PCB DRC now supports stacked alternate parts in a variant-based design.8 H( r( A( p0 A" ]/ Y
4049 Signal length column was added to Nets panel (this length is being calculated using more0 c" d, g) C R9 Q |7 [7 s( q
precise xSignal engine)- R1 u* x- Y1 h# c
4062 All extensions within a group can now be installed in a single action.1 u2 ^$ _8 `$ [0 K0 @" k
4069 Some PCB dialogs were ignoring the board units and always displaying in mils, this no longer2 r9 h$ E8 B/ k$ g( Y2 G
occurs. , Z: I" C8 `4 Y1 N9 C# I( Y" w9 i4076 Modified Polygon rule support check for shelved polygons * k4 J7 a9 }! t0 x5 [4083 During import of a P-CAD PCB file the layer types are now correctly detected and assigned for 7 z% ^5 X" k: G4 n- u4 z# m) uall possible layer configurations. 9 Y$ [8 v2 d" S4092 The DRC Violations Display page of the Preferences dialog now displays the complete list of 3 T' A. h5 p* }, NDisplay Style entries when Windows display scaling is being used. 5 Y2 v; w8 A& L* ?; d4098 An AV could occur while placing a pin in a schematic library and pressing Esc to quit the: o) D8 D0 Q$ D) M
command, this no longer happens. 0 A" n! c: U3 W2 o# g( e4111 With a specific combination of preferences, placing a component from the schematic libraries ( ]- P; N+ W) V8 J! o3 C; S5 w3 ]panel could cause Altium Designer to crash, this no longer occurs.0 A: i! |8 v/ }; z! k; K/ K
4121 After configuring components for pin swapping, it is no longer necessary for the designer to b" x- U0 \2 k3 W* H
manually recompile the design to make those swap configurations available. 1 d7 u) n# l8 O: v( x4133 Changes made in the FPGA Signal Manager are now correctly added to the constraint file.+ q# U0 b* B: ]5 b/ j, J
4135 Silk to Solder Mask design rule now correctly detects both silk to solder mask or silk to copper - A% {8 V2 V3 k) _4 Qrule check configurations. 9 L/ W E; P5 J$ h- }: n7 L; Y4215 When a polygon is shelved, connections created by the polygon are maintained internally so2 Z; r8 u! x C$ ?: T9 c' _
the connection lines will not be displayed.2 z% D0 a5 o/ `
4351 NIOS II CPU does not generates with Altera Quartus version 13.0 or later * p) n; s9 h/ B1 ASource URL: http://techdocs.altium.com/display/ADOH/Release+Notes+for+Altium+Designer+Version+15.0 : L& ~3 `5 B4 K% F. s , v, |. ?9 s; F9 V# S% P Q " D; D6 v S8 C作者: Maxim 时间: 2014-11-21 21:42
以前是一个偏执狂，一有更新就下载；; y {0 u/ h. k, N& k, H s8 \
现在我依然在用ad sumer 9；. W2 | P/ Z$ X" m+ |
本来更新的目的是消除已有的Bug，现在的更新是消掉10个Bug，带来100个Bug！作者: xuser 时间: 2014-11-26 10:22
回复看看！作者: lw3530 时间: 2014-11-26 12:47
目前在用9.4版本 14.3.13正在下载.... protel系列用过99、2004、08、09.3、09.4和短暂试用过10.几版本的忘记了作者: lw3530 时间: 2014-11-26 12:50
用AD除了对封装数量较多的库修改保存比较卡不满意外，还有就是偶尔软件会崩溃。等最新版本出来了再试试，希望体积不要太大！作者: lw3530 时间: 2014-11-26 22:34
安装试用了下AD15，第一感觉就是吃资源确实厉害，PCB里缩放已经感觉到有延迟了，跑AD9相当顺畅...看来我的机器是跑不起AD15了作者: jamesytl 时间: 2014-11-27 12:08
加泪滴后，保存到低版本，泪滴自动消掉作者: yanggo 时间: 2014-11-27 14:45
主要自己使用稳定就不要随便更新了。不尝鲜了，等你们。作者: 好人好梦 时间: 2014-11-27 16:22
用的ADsummer09，用得很好呀？干嘛还要升级，只要不出什么故障，用着顺手，管他的，更新的软件占内存越来越大，所以也不想更新作者: joeling 时间: 2015-2-25 23:23
看看是否實用...作者: jamesytl 时间: 2015-2-27 14:43
09有SUMMER和WINTER两个版本，哪个好9 a6 u; ]1 a3 f, e" O9 B1 M+ m 作者: sikixu 时间: 2016-1-19 16:26
哪里可以下载？
才看到网友说AD15出来了，然后刷微博就看到了这个。。。
rint as a single job" option in Output Job File documents now properly combines the