标题: 这段文字如何理解呢？为何会进入亚稳态？ [打印本页] 作者: mengzhuhao 时间: 2007-12-18 21:19 标题: 这段文字如何理解呢？为何会进入亚稳态？ 这段文字如何理解呢？为何会进入亚稳态？ 2 U1 A+ e8 S ^) O0 O6 B& g ! Z5 y4 R% A/ K b: [% w3 WIf the asynchronous reset is released at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.作者: mengzhuhao 时间: 2007-12-18 21:50
The biggest problem with asynchronous resets is that they are asynchronous, both at the1 ~* H8 A1 R$ ]0 h- r
assertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the' c; C3 u, K% k0 A; Q; E+ M0 h
issue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the0 z1 P0 m) z4 U4 _1 ^
output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost." x' M6 p ~ l7 y. S& L" ]8 w
Another problem that an asynchronous reset can have, depending on its source, is spurious resets5 L2 V$ U' X1 C* z7 k- {
due to noise or glitches on the board or system reset. See section 8.0 for a possible solution to; u6 P; A4 o* m4 l+ _
reset glitches. If this is a real problem in a system, then one might think that using synchronous 2 ?" ?% x2 P( nresets is the solution. A different but similar problem exists for synchronous resets if these; T6 F( q5 m; ~$ l' m& ]8 ~1 d# q
spurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is 9 {4 y6 {8 N" C! V, f3 ~( utrue of any data input that violates setup requirements).